應用在有線傳輸之分時多工離散時間差和類比數位轉換器

Abstract

隨著無線通訊的蓬勃發展，應用於無線通訊中的類比數位轉換器也受到更多 的矚目。在所有的類比數位轉換器的架構中，差和類比數位轉換器優於其他類比 數位轉換器的地方，在於擁有較佳的頻寬和解析度的經濟效益。其中，複數差和 類比數位轉換器為無線通訊中帶通差和類比數位轉換器的一種，而其產生的目的 是為了解決帶通差和類比數位轉換器在接收端對訊號做降頻時將鏡像訊號與主 要訊號同時被引入信號頻帶中的問題。此外，複數系統極點與零點不需形成共軛 複數對的特性，使得其對量化雜訊的壓抑效率優於實數系統。 在本篇論文中，我們將呈現複數差和調變器的設計流程，並將其不對稱零點 的特性應用在有線傳輸上。量測結果顯示其具有500kHz 訊號頻寬、53dB 動態範 圍及37dB 的最大訊號量化雜訊與失真比在OSR 為6 的情形下(取樣頻率為 6.125MHz)。晶片以台積電180 奈米互補式金氧半導體製程所製造，晶片面積為 1.87mm2，在1.8v 的供應電壓下消耗功率為35.6mW.

With the rapid development of communication systems, there has been more focus on analog-to-digital converter (ADC). Among all of ADCs, delta-sigma converters have better trade-off between bandwidth and accuracy. The complex delta-sigma converter is one of the band-pass delta-sigma converters in the wireless communication system to solve the issue of imaginary signal injection into signal band during down conversion. Besides, complex system can achieve better noise suppression than real counterpart since the system pole/zero need not be formed as complex-conjugate pairs. In this thesis, the design of the complex delta-sigma modulator will be presented. Its feature of the asymmetric zeros about dc is applied for wireline application. Results show for a 500-kHz signal bandwidth the ADC achieves a dynamic range of 53dB and a peak signal-to-noise and distortion ratio of 37dB with an oversampling ratio of 6 (sample rate of 6.125MHz). It was fabricated in a TSMC 0.18-μm CMOS process with a 1.87 mm2 active area, and dissipates 35.6mW from a 1.8-V power supply.