| 標題: | A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION |
| 作者: | CHEN, MJ WU, CY 交大名義發表 電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering |
| 公開日期: | 1985 |
| URI: | http://hdl.handle.net/11536/4829 |
| ISSN: | 0038-1101 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 28 |
| Issue: | 9 |
| 起始頁: | 855 |
| 結束頁: | 866 |
| 顯示於類別： | 期刊論文 |
- Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations / Ker, Ming-Dou;Hsu, Sheng-Fu
- A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES / CHEN, MJ;WU, CY
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
- 高壓BCD製程之靜電放電防護元件設計與實現 / 許哲綸;Hsu, Che-Lun;柯明道;Ker, Ming-Dou
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
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