應用於LTE無線收發器之可重組記憶體架構設計

Abstract

本論文提出並且實作以暫存器庫為基底之3GPP長期演進技術接收機平台。此平台透過shared memory pool 與 shared bus整合快速傅利葉轉換(Fast Fourier Transform)、算術邏輯單元(Arithmetic Logical Unit)兩種運算單元，以及蜂巢搜尋(Cell Search)、載波頻率偏移(Carrier Frequency Offset, CFO)、取樣時脈偏移(Sampling Clock Offset, SCO)、通道估測(Channel Estimation)和等化器(Equalizer)等通訊演算法，達到了LTE-advanced當中1024點與2048點兩種載波規格要求。使用硬體描述語言Verilog實作平台架構，並且提供足夠的擴展空間以降低未來平台的設計成本。

This thesis is proposed to the shared memory pool as based architecture of LTE modem. This architecture is combined of two computing units such as Fast Fourier Transform (FFT) and Arithmetic Logical Unit (ALU); five algorithms such as Cell Search, Carrier Frequency Offset (CFO), Sampling Clock Offset (SCO), Channel Estimation. Architecture of the LTE modem is implemented by hardware description language as Verilog, all circuits are implemented by standard-cell-based design. This architecture of modem can change or add algorithm by modifying the shared memory pool to reduce design cost.