適用於隨機處理器之動態值域偵測乘法器的分析與設計

Abstract

現今高階製程技術容易受到製程、電壓及溫度變異，造成電路行為的不確定性，使得晶片良率受到影響，大幅提高製造成本。傳統的設計方法是透過最壞情況設計，完全隱藏硬體的不確定性，這往往花費昂貴的功率消耗，在未來也將很快的不敷使用。近年來許多相關研究轉而透過隨機計算技術，允許運算錯誤的發生，但透過軟硬體技術降低錯誤的發生率及影響範圍，確保系統行為正確性。在本論文中，我們利用電路中的資料相依延遲以及乘法值域的特性，設計一動態值域偵測乘法器並且適用於隨機處理器之中。為了達到最大的省電效果，此乘法器故意放鬆合成的時序限制條件，允許錯誤的發生，特別是鮮少使用到的計算。利用值域偵測電路，偵測每一次運算中被乘數及乘數的值域，藉以修正乘積中的前導符號，大幅改善乘積的準確程度。配合軟硬體協同設計平台，可針對特定應用最佳化，以提升隨機運算效率。 最後，所建議之乘法器架構則是使用Verilog硬體描述語言來實現，再透過Synopsys Design Compiler配合UMC 65nm CMOS標準元件庫完成電路合成。至於功率消耗的估算，則是利用Synopsys PrimeTime PX EDA工具軟體進行邏輯閘層次的功率消耗估算。我們以一具有容錯機制的物件偵測器測試程式來進行模擬及數據分析。在維持與傳統乘法器同樣的人臉偵測率及操作週期的前提之下，動態值域偵測乘法器可以減少19.0%的功率消耗以及8.8%的整體面積。

In advanced technologies, severe process, voltage and temperature variations and the resulting uncertainties in the circuit behavior greatly decrease chip yields and raise manufacturing costs. Traditional IC design methodologies completely hide hardware uncertainties through worst-case design, which is often expensive in terms of power consumption and will become prohibitive in the future. In recent years, quite a few researches turn to adopt stochastic computing techniques. Computational errors are allowed while the error rate and error power are depressed using hardware and software techniques to assure correctness of system behavior. In this paper, we take advantage of data-dependent latency and multiplication range to design dynamic range detection array multiplier for stochastic processors. To achieve maximize power savings, timing constraint of the multiplier is deliberately relaxed to allow computational errors, especially for rare computation. Range of multiplicand and multiplier are utilized to estimate range of product. Influence of computation errors can thus been alleviated. With the hardware and software co-simulation platform, the multiplier can be optimized according to specific applications for improve the stochastic computation efficiency. Finally, the proposed multiplier architecture has been designed in Verilog Hardware Description Language, and synthesized using UMC 65nm CMOS standard cell library by Synopsys Design Compiler. As regards the power consumption estimation, Synopsys PrimeTime PX EDA tool was exploited to estimate the power consumption of the gate-level structures. We take a error-tolerant mechanism object detector as an example to evaluate proposed multiplier. The simulation shows the dynamic range detection array multiplier can save 19.0% power consumption and 8.8% area from conventional multiplier while maintaining the similar outcome in face detection rate and operation period.