用於三維堆疊晶片辨識的電路結構及編碼方式

Abstract

傳統半導體產業以製程微縮來降低成本與提升功能的系統晶片發展歷程已經走了數十個年頭，有越來越多的證據顯示這種型態的產業循環下一個階段將由三維整合晶片來延續，因為這項技術可製造出具有更佳效能、更低功耗與更小體積的晶片，特別是以穿矽孔為基礎的晶片堆疊技術更是目前各界發展的重點。無論是同質性或異質性的晶片堆疊，為了有效控制或管理三維晶片內部的溫度，或是使用共通的穿矽孔匯流排，並非每一層的晶片在同一個時間點都在運作。例如，將DRAM晶片堆疊一起，若是讓上下相鄰的DRAM晶片同時操作，內部溫度可能會超過DRAM晶片所能容忍的攝氏85度；又例如在共通的穿矽孔匯流排上輸出資料，為避免資料衝突，必須保證負責輸出資料的晶片為啟動但其他晶片不啟動等。因此必須在溫度與效能的考量下，整體規畫各層晶片的啟動條件，但要能夠控制那一層晶片運作與否，需要先知道該晶片所在的位置，因此三維堆疊晶片的辨識方法就有其存在的必要性。本論文提出一種用於三維堆疊晶片辨識的電路結構與編碼方式，每組結構由一個穿矽孔與一個可程式化的訊號交換電路所組成，使用一組或以上這樣的結構，並將每組結構的輸出端共同連接至一個邏輯解碼電路，就可以此解碼電路的輸出作為該層晶片的選擇訊號，最後以特定的順序進行堆疊，使其可以藉由不同的識別訊號來對每一層晶片進行識別，使用N組這樣的結構可以作為2N層堆疊晶片的識別。以本論文提出的方法所設計的測試晶片也參與了國內首次的三維晶片多專案晶圓下線計畫，電路部分使用了台灣積體電路公司的0.18µm製程，後段則使用了工業技術研究院的後穿矽孔與面對背堆疊製程，並完成了測試晶片的封裝與測試的作業。

The traditional semiconductor sector has successfully applied process technology miniaturization to improve both cost and performance for several decades; however, such conventional scaling is gradually approaching the physical limit. To continue the march of Moore’s Law in the future, 3-D integration technology has shown the most promise among other technology alternatives. Through die stacking using through silicon vias (TSV), 3-D integrated circuits (or 3-D IC) can further improve the performance and lower the overall power consumption of a system while simultaneously achieving a more compact form factor. Regardless of homogeneous or heterogeneous die stacking, in order to effectively manage the temperatures inside a 3-D IC or use the common TSV buses for data output, not every layer of the chip are in operation at the same time. To control the correct operation of each die layer, one needs to know the exact die location where the function to be performed is located. In other words, it becomes necessary to identify chip functions and their respective die layer locations inside a 3-D IC. In this thesis, we propose new logic circuit structure and coding method to enable die layer identification in 3-D IC. Our structure is composed of one TSV and one programmable signal TSV switch circuit. By employing one or more such structures and connecting their output terminals to a common logic decoder, the output signals of the decoder can be used as the identification code for selecting each die layer. With a specific 3-D die stacking order, a die layer can easily be identified. Using N sets of such structure, our technique can successfully identify a 3-D chip stacked up with 2N layers. The test chip based on our proposed mechanisms was designed and fabricated via the very first 3D multi-project-wafer run in Taiwan. The logic die was fabricated by Taiwanese Semiconductor Manufacturing Corporation using 0.18µm technology node while the backend process including TSV fabrication and face-to-back stacking was performed at Industrial Technology Research Institute. The final test chip was also packaged and tested.