使用電阻回授與串聯峰化電感之超寬頻低雜訊放大器

Abstract

本篇論文為討論超寬頻低雜訊放大器之設計和分析。此超寬頻低雜訊放大器同時具有高增益、高線性度、低雜訊、低功率和面積小等優點。超寬頻低雜訊放大器是以TSMC 0.18μm CMOS 1P6M設計製作，採用疊接式電阻回授式架構並使用串聯峰化電感提升頻寬和增益。第一部份，輸入網路使用帶通LC濾波器實現寬頻匹配，第二部分則為使用電阻回授(Resistive feedback)和串聯電感峰化技術(Series inductive peaking)來增加頻寬和高頻增益。經量測，低雜訊放大器的頻寬涵蓋UWB 3.1GHz ~ 10.6GHz，在頻段內增益為8 ~ 12.5 dB，雜訊指數為2.9 ~ 4.3 dB，輸入反射係數小於 -10.0 dB，輸出反射係數小於 -10.0 dB，在頻率為6.8GHz時三階截斷點(IIP3)為+5.0 dBm，增益壓縮點(P1dB)為-5.5 dBm，電路的工作電壓為1.5 V，功率消耗為18 mW。整個電路面積包含pad為0.68mm2。

This thesis discusses the design and analysis of an ultra wideband low noise amplifier. It has the advantage of high gain, high linearity, low noise, low power consumption and small chip size. The ultra wideband low noise amplifier was implemented in TSMC 0.18 um CMOS technology and based on the cascode resistive feedback architecture with bandwidth extension by series peaking inductor. The first part introduces series LC band pass filter to achieve input matching. The second part introduces resistive feedback with series inductive peaking configuration to extend bandwidth and gain. The measured bandwidth of the low noise amplifier covers UWB 3.1-10.6GHz and within this band the gain is 8 ~12.5 dB, the noise figure is 2.9 ~ 4.3 dB, the input return loss is below -10.0 dB, the output return loss is below -10.0 dB. The input third intercept point(IIP3) measured at 6.8GHz is +5.0 dBm, the input power at 1dB gain compression point(P1dB) at 6.8GHz is -5.5 dBm. This low noise amplifier consumes 18 mW from a 1.5 V power supply. The chip size included pad is 0.68 mm2.