1.8伏金氧半低雜訊放大器應用於超寬頻3.1-10.6GHZ無線接收端

Abstract

本論文研製一個應用於超寬頻3.1-10.6 GHZ的低雜訊放大器是採用電感-電容階梯式做輸入匹配，而在輸出端是用L-section做匹配。本研究是以0.18微米互補式金氧半製程實現。此低雜訊放大器是以兩級放大為主架構，第一級為CS-CG 堆疊結構，是為了改善逆向隔離S12及頻率響應，第二級為Darlington pair結構，可以增加單位增益頻寬fT。為了能在所應用的頻段內達到相對的平坦增益，利用shunt peaking 的方法去實現。供應電壓VDD為1.8伏特時，整個電路功率消耗約為22mW，及包含pad的情況下整個電路大小約為1 mm2。本研究的低雜訊放大器所量測的規格，平均順向增益(S21)約為7dB，逆向隔離(S12)約為-35dB，S11約為-7dB，S22約為-8dB。而平均雜訊指數約為8dB。

A 3.1-10.6 GHZ low noise amplifier is applied for ultra-wideband, it introduces LC ladder for input matching. And L section is used for output matching. This research is fabricated in 0.18-μm CMOS process. Two amplified stages are formed for main topology in low noise amplifier. The first stage introduces CS-CG cascode configuration, it can improve the reverse isolation and frequency response. The second stage introduce Darlington pair configuration, it can boost the unity gain bandwidth. Relatively flat gain is essential over the entire desired band. The low noise amplifier introduces the shunt peaking to achieve the above purpose. The total power dissipation of the chip is about 22 mW at power supply 1.8 volt. The chip size included pad is 1 mm2. The measurement result of this study expect that the average forward S21 is 7 dB, the reverse isolation S12 is -35 dB, the magnitude of S11 is -7 dB, the magnitude of S22 is -8 dB, and the noise figure is 8 dB.