可調式增益之低雜訊CMOS混頻器設計應用於C-Band微波系統

Abstract

本論文主要是討論泛用於4 ~ 8GHz系統之接收寬頻高增益低雜訊混頻器的設計。在接收機的設計中，大部份的設計均使用低雜訊放大器來控制雜訊係數(Noise Figure)，並且有著高增益來壓制後級所產生的雜訊，因此研究方向著重於降低混頻器的雜訊係數，讓系統可省略低雜訊放大器之設計，已達到節省主動元件所耗電流以及面積。 此高增益低雜訊混頻器電路設計應用於4 ~ 8GHz接收機，使用"偶次諧波混頻器"的電路架構。該降頻器輸入頻段為4 ~ 8GHz，利用LO訊號為3.7 ~ 7.7GHz，將此頻段的訊號降頻到DC~300MHz。電路實驗結果，最大功率轉換增益為27.5dB及8.2dB的雜訊係數。在1.8伏特的操作電壓下，其總功率消耗為7.02毫瓦。 本篇論文之電路設計採用TSMC 0.18微米混合訊號互補式金氧半導體製程，此混頻器採用on-wafer的方式量測，其實驗結果符合設計目標並適用於消防署、802.11a (5.2GHz)、ISM頻帶(5.725 ~ 5.850GHz) 、航空局相關系統的應用。

This microwave wideband high-gain low noise CMOS Mixer design for 4 ~8GHz applications are presented in this thesis. In the receiver circuits design, the most of the low noise amplifier to control the noise coefficient (Noise Figure), and has a high gain to suppress noise. The research focuses on reducing the Mixer’s noise figure. The system can omit the low noise amplifier design has been to save the active components of the current consumption and chip area. This high-gain low noise Mixer circuit design applied to 4 ~ 8GHz receiver, the “even harmonic Mixer circuit” architecture. The down-converter input frequency band to 4 ~ 8GHz , LO signal for the 3.7 ~ 7.7GHz, this band signal down-conversion to DC ~ 300MHz. Circuit experimental results, the maximum power conversion gain of 27.5dB and 8.2dB noise figure. Operating voltage of 1.8 volts, the total power consumption is 7.02mW. In this thesis, the circuit design using TSMC 0.18μm mixed-signal complementary metal oxide semiconductor process, the Mixer with on-wafer measurements, the experimental results meet the design goals for the Fire Services Department,802.11a (5.2GHz), the ISM band (5.725GHz ~ 5.850GHz), Civil Aviation Bureau related systems.