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dc.contributor.author陳慧燕en_US
dc.contributor.authorChen,Hui-Yenen_US
dc.contributor.author吳耀銓en_US
dc.contributor.authorWu,Yew-Chungen_US
dc.date.accessioned2014-12-12T01:54:08Z-
dc.date.available2014-12-12T01:54:08Z-
dc.date.issued2012en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079875506en_US
dc.identifier.urihttp://hdl.handle.net/11536/48838-
dc.description.abstract本論文之研究為 0.15um 高壓元件閘極氧化層之膜厚均勻度改善研究。一般閘極氧化層是使用熱氧化(thermal oxidation)製程方式,熱氧化製程須克服矽底材之熱應力分布。於本論文研究熱氧化製程藉由晶圓於爐管擺放位置的最佳化、熱氧化方式、高溫回火方法以及犧牲氧化層蝕刻來改善閘極氧化層膜厚均勻度。 結果發現高溫回火方式由快速升溫法(RTP)改變為傳統爐管回火最為有效,但因高壓元件的熱預算考量最終使用犧牲氧化層蝕刻來改善閘極氧化層膜厚均勻度。zh_TW
dc.description.abstractThe purpose of this study is to improve the uniformity of gate oxide thickness in 0.15μm high voltage device. Thermal oxidation process was used to fabricate this gate oxide. During oxidation process, gate oxide needs overcome the thermal stress distribution caused from the Si substrate. In this paper, the uniformity of gate oxide thickness was improved through investigation of the position of the wafer, oxidation method, annealing method and “sacrifice etching” of oxide layer. Change annealing method from RTA to furnace can improve this issue but the thermal budget concerned high voltage device. The sacrifice etching of oxide is the final solution.en_US
dc.language.isozh_TWen_US
dc.subject熱氧化zh_TW
dc.subject閘極氧化層zh_TW
dc.subject回火zh_TW
dc.subjectthermal oxidationen_US
dc.subjectGate Oxideen_US
dc.subjectAnnealen_US
dc.title高壓元件閘極氧化層膜厚均勻度之改善zh_TW
dc.titleImproved the uniformity of Gate Oxide Thickness of High Voltage Devicesen_US
dc.typeThesisen_US
dc.contributor.department工學院半導體材料與製程設備學程zh_TW
Appears in Collections:Thesis