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dc.contributor.author黃稚銨en_US
dc.contributor.authorHuang, Chih-Anen_US
dc.contributor.author吳耀銓en_US
dc.contributor.authorWu, YewChung Sermonen_US
dc.date.accessioned2014-12-12T01:54:08Z-
dc.date.available2014-12-12T01:54:08Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079875525en_US
dc.identifier.urihttp://hdl.handle.net/11536/48847-
dc.description.abstract二十一世紀的科技發展將環繞在資訊處理與能源節約上,隨著半導體製程技術的蓬勃發展,如何有效節省能源,又能快速進行資訊處理,需要依賴有省能效果且大容量的電力電子切換元件。因此,功率半導體元件技術的發展,將扮演舉足輕重的角色。 本研究係探討在半導體製程實務面上所遭遇到的問題,針對研究對象「非對稱性高壓FD-MOSFET元件(Asymmetric High Voltage Field Diffusion Metal-Oxide-Semiconductor Field-Effect Transistor)」,其在實務上量產晶片(On silicon)的「臨界電壓(Vt)」(Threshold voltage) ,表現出的趨勢(Roll off)行為與SPICE model的表現不一致。然而,On silicon與SPICE model兩者的匹配,一直是半導體業界極為重要且必須解決的課題。如此才能提供高效能的功率半導體元件,以符合並滿足IC設計者設計電路及元件的需求。 故本論文之研究重點在於利用特性要因分析方法(Cause-Effect Diagram)進行要因分析,找出造成非對稱性FD-MOS元件之臨界電壓於SPICE model與on-silicon不匹配的真因,並經由適當的實驗設計得出兩者不匹配的原因,進而提出有效的解決方案。實驗結果顯示, 藉由本研究所提出的解決方案能使得非對稱性FD-MOS元件之臨界電壓於SPICE model與on-silicon達成匹配的結果。zh_TW
dc.description.abstractTechnology development in the twenty-first century will be surrounded with information processing and power saving. As the technology of semiconductor manufacture grows vigorously, how to save the power efficiently and to process with information quickly, a power-saving and high-capacity electric power-switching device is needed. Therefore, power semiconductor device technology will play a decisive role in the future. It will be discussed about the issue suffered from the semiconductor manufacture in this research, i.e. the mismatch of threshold voltage roll off behavior between on-silicon and SPICE model in “Asymmetric High Voltage Field Diffused MOSFET” device. However, the matching results between on-silicon and SPImodel is always a very important task and need to be solved in semiconductor industry. In this way, high-efficiency power semiconductor device can be provided to fit and meet the demand of IC designers in circuit and device design. Therefore, the analysis of root cause by cause-effect diagram will be emphasized in this thesis, in order to find out the true reason of the mismatch in threshold voltage between SPICE model and on-silicon asymmetric FDMOS device. Then through the proper experiment design to confirm the root cause and propose an effective solution further. From the experimental results, it’s shown that the threshold voltage of asymmetric FDMOS device between SPICE model and on-silicon seems to be comparable by the method suggested in this investigation.en_US
dc.language.isozh_TWen_US
dc.subject金氧半場效電晶體zh_TW
dc.subject高壓zh_TW
dc.subjectMOSFETen_US
dc.subjectHVen_US
dc.title利用特性要因分析法改善場擴散金氧半場效電晶體製程zh_TW
dc.titleImprovement of the Fabrication Process of Field Diffusion Metal-Oxide-Semiconductor Field-Effect Transistor using Cause-Effect Diagramen_US
dc.typeThesisen_US
dc.contributor.department工學院半導體材料與製程設備學程zh_TW
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