微影製程覆蓋誤差控制

Abstract

黃光微影製程控制的幾個要項中，覆蓋誤差(Overlay Error)是重要的項目之一，覆蓋誤差的量測結構為Box-in-Box結構。在晶圓製作時，前層結構位於外圍大的盒框，本層結構為內部小的盒框。藉由量測這兩個盒框的相對位置來判斷本層與前層間的覆蓋誤差，而覆蓋誤差的大小可以透過Overlay控制的10個機台製程參數來呈現。

本論文主要目的為微影製程晶圓曝光流程細對準(Global Alignment)步驟時，藉由不同Alignment Mark(對準標記)的選擇，找出最適合的Mark，來減少實際Run貨時Lots(貨)間量測之覆蓋誤差值過大的問題。本論文先將光罩設計(Mask Layout)完成之Alignment對準Mark列出，以Run貨方式做資料分析，找出最適於本評估Layer的Alignment Mark。並於找出最適當Mark之後，變更Run貨Recipe(程式)，實際下貨驗證，比較變更前後Overlay量測之殘值Residual (X & Y方向不可線性補償之覆蓋誤差)、X Mean + 3 sigma、Y Mean + 3 sigma及Overlay控制的10個製程參數，確認經此實驗之後，藉由不同Mark的選擇，可以得到良好的覆蓋誤差量測值，使覆蓋誤差控制能力獲得改善。

本論文另一評估項目是覆蓋誤差量測Mark評估，Overlay量測Mark在量測時選擇微影與蝕刻製程完Overlay量測上差異最小的Mark，為最適當的量測Mark，並變更Run貨Recipe，藉由量測資料驗證以得到良好的覆蓋誤差控制。

In semiconductor manufacturing process, the overlay error is an important issue in photolithography process control. This overlay error is generated by Box-in-Box structure variation in measurement process. For wafer manufacture, pre-layer of the chips is located on the outside area of big box frame, the present-layer of the chips is located in the inside area of small box frame. Due to the measurement process change, these two box frame's relative positions are different, and cause the overlay error from the present-layer to pre-layer. The improvement of overlay error is controlled by 10 parameters.

The purpose of this thesis is for global alignment step of wafer exposure flow in lithography process. To reduce overlay error, a suitable alignment mark is chosen from the actual operation experiments. Different alignment marks are evaluated by completing the mask layout and analyzing the data of actual samples run to discover most suitable alignment mark at this layer. After discovering a most suitable mark, operation recipe is changed and verified. Comparing the overlay measuring residuals, X Mean + 3-sigma, Y Mean + 3-sigma, and the overlay control 10 parameters, the experiment confirmed that the alignment mark affects overlay error measured data, and influences the ability of overlay error control.

Another experiment is overlay error measurement mark estimation. The lithography process and etching process is to discover a smallest measurement mark. For most suitable measuring mark obtained by experiment, the operation recipe is revised.