标题: 微影制程覆盖误差控制
Overlay Error Control of Lithography Process
作者: 詹孟勋
Cha, Meng-Hsun
郑泗东
Cheng, Stone
平面显示技术硕士学位学程
关键字: 覆盖误差;Overlay Error
公开日期: 2011
摘要: 黄光微影制程控制的几个要项中,覆盖误差(Overlay Error)是重要的项目之一,覆盖误差的量测结构为Box-in-Box结构。在晶圆制作时,前层结构位于外围大的盒框,本层结构为内部小的盒框。藉由量测这两个盒框的相对位置来判断本层与前层间的覆盖误差,而覆盖误差的大小可以透过Overlay控制的10个机台制程参数来呈现。

本论文主要目的为微影制程晶圆曝光流程细对准(Global Alignment)步骤时,藉由不同Alignment Mark(对准标记)的选择,找出最适合的Mark,来减少实际Run货时Lots(货)间量测之覆盖误差值过大的问题。本论文先将光罩设计(Mask Layout)完成之Alignment对准Mark列出,以Run货方式做资料分析,找出最适于本评估Layer的Alignment Mark。并于找出最适当Mark之后,变更Run货Recipe(程式),实际下货验证,比较变更前后Overlay量测之残值Residual (X & Y方向不可线性补偿之覆盖误差)、X Mean + 3 sigma、Y Mean + 3 sigma及Overlay控制的10个制程参数,确认经此实验之后,藉由不同Mark的选择,可以得到良好的覆盖误差量测值,使覆盖误差控制能力获得改善。

本论文另一评估项目是覆盖误差量测Mark评估,Overlay量测Mark在量测时选择微影与蚀刻制程完Overlay量测上差异最小的Mark,为最适当的量测Mark,并变更Run货Recipe,藉由量测资料验证以得到良好的覆盖误差控制。
In semiconductor manufacturing process, the overlay error is an important issue in photolithography process control. This overlay error is generated by Box-in-Box structure variation in measurement process. For wafer manufacture, pre-layer of the chips is located on the outside area of big box frame, the present-layer of the chips is located in the inside area of small box frame. Due to the measurement process change, these two box frame's relative positions are different, and cause the overlay error from the present-layer to pre-layer. The improvement of overlay error is controlled by 10 parameters.

The purpose of this thesis is for global alignment step of wafer exposure flow in lithography process. To reduce overlay error, a suitable alignment mark is chosen from the actual operation experiments. Different alignment marks are evaluated by completing the mask layout and analyzing the data of actual samples run to discover most suitable alignment mark at this layer. After discovering a most suitable mark, operation recipe is changed and verified. Comparing the overlay measuring residuals, X Mean + 3-sigma, Y Mean + 3-sigma, and the overlay control 10 parameters, the experiment confirmed that the alignment mark affects overlay error measured data, and influences the ability of overlay error control.

Another experiment is overlay error measurement mark estimation. The lithography process and etching process is to discover a smallest measurement mark. For most suitable measuring mark obtained by experiment, the operation recipe is revised.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079887502
http://hdl.handle.net/11536/48895
显示于类别:Thesis