完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yang, WL | en_US |
dc.contributor.author | Lin, CJ | en_US |
dc.contributor.author | Chao, TS | en_US |
dc.contributor.author | Liu, DG | en_US |
dc.contributor.author | Lei, TF | en_US |
dc.date.accessioned | 2014-12-08T15:01:42Z | - |
dc.date.available | 2014-12-08T15:01:42Z | - |
dc.date.issued | 1997-06-19 | en_US |
dc.identifier.issn | 0013-5194 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/488 | - |
dc.description.abstract | A method is introduced for suppressing the penetration of boron for BF2+-implanted pMOS devices with a stacked amorphous/ poly-Si (SAP) gate structure. It is shown that after inductive-coupling-nitrogen-plasma (ICNP) treatment, boron diffusion through the thin gale oxide is largely suppressed. As shown from the charge-to-breakdown measurements, the ICNP process will improve the quality of pMOS devices, with Q(bd) three times higher than for the control samples. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | MOS integrated circuits | en_US |
dc.subject | plasma | en_US |
dc.title | Suppression of boron penetration by using inductive-coupling-nitrogen-plasma in stacked amorphous/polysilicon gate structure | en_US |
dc.type | Article | en_US |
dc.identifier.journal | ELECTRONICS LETTERS | en_US |
dc.citation.volume | 33 | en_US |
dc.citation.issue | 13 | en_US |
dc.citation.spage | 1139 | en_US |
dc.citation.epage | 1140 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000072040900027 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |