利用介面鈍化與電漿處理對原子層沉積二氧化鉿/砷化銦金氧半電容之研究

Abstract

在這篇論文中，首先我們研究了在原子層沉積主要高介電常數絕緣層前利用前驅物做”自我清潔”的預處理，其中有三氧化二鋁的前驅物-三甲基鋁[TMA, Al(CH3)3]，以及二氧化鉿的前驅物-四(乙基甲基氨基)鉿[Hf(N(C2H5)(CH3))4]。之後沉積不同的閘極介電層，分別是三氧化二鋁以及二氧化鉿，和前驅物預處理採用排列組合方式選出三種閘極介電層。並藉由二種後沉積熱過程，後沉積退火400度120秒以及300度30分鐘氫氣氮氣混合之熱退火。我們發現利用後沉積退火對於成長不同高介電常數絕緣層之砷化銦金氧半電容電性上並無明顯的趨勢，反之利用300度30分鐘氫氣氮氣混合之熱退火則大幅改善了各種高介電常數絕緣層以及絕緣層/砷化銦介面的品質。三種不同的閘極介電層各經過300度30分鐘氫氣氮氣混合之熱退火，三甲基鋁[TMA, Al(CH3)3]前驅物預處理/二氧化鉿閘極介電層擁有最佳化的電性條件，並且將此閘極介電層繼續進行下一步的電漿研究。 其次，我們研究了在原子層沉積閘極介電層中加以不同次數之氧氣電漿處理，觀察其對二氧化鉿/砷化銦金氧半電容電性之影響。我們發現當採用高次數電漿處理時，二氧化鉿/砷化銦金氧半電容在聚積、空乏、以及反轉區域有比較小的頻率分散現象，表示其對於閘極介電層以及閘極介電層/砷化銦介面的品質有較好的改善能力。再經過300度30分鐘氫氣氮氣混合之熱退火則可以進一步改善閘極介電層以及介電層/砷化銦介面的品質。 最後，我們利用建立一個閘極介電層內缺陷的模型解釋基板在操作大閘極偏壓下其費米能階附近的電子和閘極介電層內缺陷的穿隧機制。利用此模型所計算出的參數和實驗所得的多重頻率下電容-電壓與電導-電壓數據做媒合，可以定量地萃取出在閘極介電層內的缺陷密度-單位為體密度而非傳統介面捕捉缺陷密度-面密度。

In this thesis, first of all, we investigated the “self-cleaning” pretreatment before the main high-k dielectric in atomic-layer-deposition system, by the precursor of Al2O3 - trimethyl aluminum [TMA, Al(CH3)3], and the precursor of HfO2 - tetrakis(ethylmethylamino)hafnium [TEMAH, Hf(N(C2H5)(CH3))4]. Then the high-k dielectrics, Al2O3 and HfO2 with precursors trimethyl aluminum [TMA, Al(CH3)3] and tetrakis(ethylmethylamino)hafnium [TEMAH, Hf(N(C2H5)(CH3))4] were chosen three gate dielectrics by the way of permutation and combination. And we applied two post-deposition thermal processes, post deposition annealing (400°C/120s) and forming gas annealing (300°C/30min.). We found that there was not clear trend for InAs MOS capacitors with different high-k dielectrics in post deposition annealing. However, adopting forming gas annealing, the obvious improvement on high-k dielectrics and high-k dielectric/InAs interface quality was observed. For three different gate dielectrics, all of them in forming gas annealing (300°C/30min.), TMA/HfO2 gate dielectric has the optimum electrical properties. Then, we utilized this dielectric to further research in plasma treatments. Secondly, we investigated the effects on the HfO2/InAs MOS capacitors by various numbers of times in plasma treatments during the process of atomic-layer-deposition. It is observed that there are weak frequency dispersion in the regions of accumulation, depletion, and inversion, by using higher times of plasma treatment. This represented that the ability of improving high-k dielectrics and high-k dielectric/InAs interface quality is great for high plasma density treatment. By applying forming gas annealing (300°C/30min.), the high-k dielectrics and high-k dielectric/InAs interface quality were further improved. Finally, we built up a model to explain the tunneling mechanism between the electrons near Fermi level of the substrate and traps in the gate dielectric which is operated at high gate bias. We fitted the calculations of the model with experimental data, multi-frequency C-V and G-V, and then we could quantitatively extract the traps density in the gate dielectric, which is in unit of volume density. Unlike interface state, is in unit of areal density.