奈米尺度多重閘極金氧半場效電晶體之靜態隨機存取記憶體的設計與分析特性

Abstract

本論文包含了兩個主題並如同下面的方式排列。第一，我們提出了三種應用於奈米尺度Bulk-CMOS技術下的電流拴鎖型感應放大器 (Current-Latch-based Sense Amplifier) 以及多種運用獨立閘極控制 (independently-controlled-gate) 鰭狀場效電晶體 (FinFET) 的電流拴鎖型感應放大器。第二，我們在TCAD平台上提出了一個用來模擬奈米線狀場效電晶體 (Nanowire MOSFET)二維線邊緣粗糙程度 (Line Edge Roughness) 的方法。上述的兩個研究成果將在第二及第三段做簡單的描述。

在第一個研究中，由廣泛的模擬結果可得知我們提出的架構非常堅固，可抵抗隨機補償錯誤。我們提出的電流拴鎖型感應放大器可以大幅壓抑補償電壓的能力，在40nm Bulk-CMOS (25nm FinFET-SOI) 的技術下與傳統電流拴鎖型感應放大器比較，補償電壓的變異最高可以有74% (76%)的降低。同時，可以最多減少27% (52%) 的感應時間，以及可以最多少71% (77%) 的Time-To-Sense時間，bit-line的功率消耗可以降低73% (76%)。最後我們提出的電流拴鎖型感應放大器可以大幅的提升感應良率，一條bit-line可承受的cell個數，因此強化了array的使用效率、全部面積、表現能力和功率。

在第二個線狀場效電晶體的研究中，我們提出來的方法相較於先前文獻所使用的兩種一維型態變異[1]可以更精確的預測元件特性和變異。根據所提出來的模擬方法，我們運用了三維TCAD模擬器和蒙地卡羅 (Monte Carlo) mixed-mode 模擬在Wire-LER變異性對元件特性、操作在次臨界區6T SRAM及邏輯電路穩定性的衝擊上做了完整的分析。以上的結果皆會與先前文獻的方法做比較來顯示出用一維型態變異的模型和預測的不足。

This thesis contains two topics and is organized as follows. First, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Second, a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs is proposed in TCAD platform. The simple description of above two topics is arranged in the second and third paragraph separately.

In the first work, extensive simulations suggest the proposed CLSAs are robust against random offset errors. The proposed structures feature significant offset suppression capabilities with σoffset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.

In the second study in NW MOSFETs, the proposed approach predicts the device characteristic and variations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.