High-k/Metal Gate 與 SOI金氧半場效電晶體RTN分析與可靠度的研究

Abstract

近年來積體電路隨著摩爾定律的微縮,增加了單位面積中的電晶體密度，降低製程成本提高了IC的運作效率。雖然電晶體的微縮增加了IC元件的性能與經濟的效益，但其中還是必須去克服幾個問題：1.隨著定電場微縮的過程中，必須降低閘極氧化層SiO2 的厚度，如此會導致閘極漏電並造成能量的消耗。2.隨著電晶體微縮至深次微米尺度，其必須面對短通道效應與物理微縮的極限。因此未來的ULSI元件而言也提出了先進的技術到CMOS製程當中，克服了能量的消耗以及元件的運作效率的問題，其中包括了SOI元件以及high-k/metal gate製程技術。 當元件微縮至深次微米尺度時，RTN(或著稱作RTS)可探討元件的缺陷位置以及電性上的分析。隨著元件尺寸的微縮，在元件氧化層的費米能階附近有機會存在單顆或是數顆的缺陷，並且可由RTN來深入的觀察，在此我們藉由RTN去探討SOI與high-k/metal gate元件去做一個深入的討論。

In the past years, chips complexity have increased at an exponential rate, because of the constant shrinking of device size to increase device density, improved manufacturing practice to reduce fabrication cost and increase IC’s performance. Although scaling devices can improve IC’s performance and be economically fabricated, it still have to overcome some issues. First, when devices scaled down it have to follow the constant electric field, so the thickness of gate dielectric, namely SiO2 need to be lessened. This will increase gate leakage current and lead to more power dissipation. Secondly, when scaling device down to deep sub-micrometer, MOSFETs face short channel effect and physical scaling limit. Therefore, for the future ULSI devices, there are some advance technology have been proposed and introduced into CMOS fabrication process to achieve higher performance and lower power consumption, which includes silicon-on-insulator (SOI) technology and high-k/metal gate stack technology. When devices scaled down to deep sub-micrometer the random telegraph noise (RTN) or so-called random telegraph signal (RTS) will be observed and influence device dynamic performance. In deep sub-micrometer MOSFETs, it is possible to exist one or few oxide traps in high-k or SiO2 layer which were distributed over the vicinity of Si surface Fermi level. These traps can be investigated by RTS. In this article, we use RTN to focus on high-k/metal gate and silicon-on-insulator device to research electrical characteristics.