完整后设资料纪录
DC 栏位语言
dc.contributor.author廖伟男en_US
dc.contributor.authorLiao, Wei-Nanen_US
dc.contributor.author庄景德en_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-12T01:55:03Z-
dc.date.available2014-12-12T01:55:03Z-
dc.date.issued2012en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079911526en_US
dc.identifier.urihttp://hdl.handle.net/11536/49074-
dc.description.abstract近几年来,记忆体在许多电子产品中被广泛运用,因为记忆体的高操作速度与高效能。另外,因为静态随机存取记忆体也比其他种类的记忆体具有更高的操作速度,所以静态随机存取记忆体在高性能微处理器的快取记忆体和嵌入式系统中更是被广泛应用。过去20年间,6T 静态随机存取记忆体因为有较高的操作速度与较紧密的面积,因此在设计上仍然以6T静态随机存取记忆体为设计主流。但是随着制程演进至深次微米等级之后,制程变异会是影响6T静态随机存取记忆体存活的关键因素。在先进制程下,这些制程变异会让6T 静态随机存取记忆体的读或写的能力受到严重的退化。除了读写能力受到影响之外,特别是在低压操作时,6T 静态随机存取记忆体几乎是无法正常的运作。
为了设计出能在先进制程下正常运作的6T 静态随机存取记忆体,我们提出三步阶升压型字元线技术、适应性数据感知写入辅助技术、位元线降压技术以及适应性电压侦测技术来提高读写能力与降低闸极氧化层被击穿的机会。此外,为了提高操作速度我们也运用管线化技巧。在本论文中,我们将这些技术、2阶级管线化技术与单电源电压设计在一颗1.0Mb高性能6T 静态随机存取记忆体,并且透过下线将该晶片实现在40奈米低功耗互补金属氧化物半导体技术上。该晶片可以工作在宽电压范围从 1.2V至0.7V,具有工作平率900MHz@1.1V 和 25oC。
zh_TW
dc.description.abstractIn recent years, memories have been widely used for the most electronic products due to their high operation speed and high performance. Besides, Due to SRAMs have higher operating speed than other memory family, SRAMs have been widely used for the high-performance microprocessor cache and embedded system. During the past 20 years, standard 6T SRAM cell becomes the mainstream of SRAMs design due to its highest speed and compact area. However, with the scaling into the deep sub-micron of process, the process variation affects the subsistence of the 6T SRAM cell. In advance technology node, the read and write ability suffer a serious degradation by theses process variation. Especially, at low operation voltage, 6T SRAM cell almost couldn’t have normal operation.
In order to design the 6T SRAM that it can normal work in the advanced process, we proposed the Three Step-Up Word-Line technique, Adaptive-Data-Aware Write-Assist technique, Bit-Line Under-Drive Read-Assist technique, and Adaptive Voltage Detector technique to enhance the read/write ability and performance, and reduce the gate oxide to be punctured. Besides, in order to enhance operating speed, we also applied the pipeline technique to enhance the operating speed. In the thesis, we design a 1.0Mb high-performance 6T SRAM with these techniques with two stage pipeline technique with a single supply voltage, and implement by way of tape out in the 40nm Low- Power complementary metal-oxide semiconductor technology. The chip has wide voltage range from 1.5V to 0.6V, with operating frequency of 900MHz@1.1V and 25℃.
en_US
dc.language.isoen_USen_US
dc.subject静态随机存取记忆体zh_TW
dc.subject管线化zh_TW
dc.subject三步阶升压型字元线zh_TW
dc.subject位元线降压zh_TW
dc.subject适应性电压侦测zh_TW
dc.subjectStatic Random Access Memory (SRAM)en_US
dc.subjectPipelineen_US
dc.subjectThree Step-Up Word-Lineen_US
dc.subjectBit-Line Under-Driveen_US
dc.subjectAdaptive Voltage Detectoren_US
dc.title40奈米1.0Mb 6T管线化静态随机存取记忆体与三步阶升压型字元线和位元线降压和适应性电压侦测zh_TW
dc.title40nm 1.0Mb 6T Pipeline SRAM with Three Step-Up Word-Line, Bit-Line Under-Drive and Adaptive Voltage Detectoren_US
dc.typeThesisen_US
dc.contributor.department电子研究所zh_TW
显示于类别:Thesis


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