具鎳矽化物源汲極之多晶矽奈米線互補式金氧半反相器元件的製程與特性分析

Abstract

在本篇論文中，我們利用本實驗室所發展出一簡單且低成本方法製作多晶矽奈米線通道薄膜電晶體，並經由製程步驟上些許的修改，完成一個具有側向閘極結構的多晶矽奈米線通道之互補式金氧半反相器。所提出的反相器其n型與p型通道薄膜電晶體是使用邊襯(sidewall spacer)蝕刻技術，形成多晶矽奈米線通道。不同於傳統的互補式金氧半反相器製作，通常對n型與p型的源極與汲極形成是需要兩道光罩的離子植佈步驟，而我們所提出的反相器巧妙地利用斜角度離子植佈方式，僅需一道光罩即可完成源極與汲極離子植佈步驟。 然而，根據初始的基本電性特性量測發現，因源極與汲極的高串聯電阻造成n型與p型通道薄膜電晶體的低導通電流，因此將鎳矽化物步驟引進製程來改善高串聯電阻之問題。藉由加入鎳矽化物製程所造成的結構與製程上的修改，不但使得極與汲極的高串聯電阻問題被消除，也使得反相器的電性特性獲得改善。在本篇論文中，我們亦研究實行氨氣電漿處理對反相器之n型與p型通道薄膜電晶體的影響。

In this thesis, we employed a simple and low-cost method previously developed by our group to fabricate NW-channel TFTs. With a slight modification in the fabrication procedure, a novel poly-Si NW-channel CMOS inverter with side-gated configuration was fabricated and characterized. The n- and p-channel TFTs of the proposed inverter use the sidewall-spacer etching technique to form their poly-Si NW channels. Unlike conventional CMOS inverters which usually require two separate masking implantation processes for n- and p-type S/D formation, respectively, the proposed inverter ingeniously incorporated a one-mask-only S/D implantation process utilizing a clever title-angle implantation approach. However, from the preliminary examination of the basic electrical properties, low ON-currents resulted by the high series S/D resistance for both n- and p-channel TFTs were revealed. Therefore, Ni silicidation process was implemented in the fabrication to improve the series resistance issue. With the structural and process modifications by adding Ni silicidation process in this work, not only the series resistance of S/D issue was reduced, but also the electrical characteristics of the fabricated inverters were improved. In addition, the effects of implementing NH3 plasma treatment for n- and p-channel TFTs of the fabricated inverters have also been analyzed in this thesis.