Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 周涵宇 | en_US |
dc.contributor.author | Chou, Han-Yu | en_US |
dc.contributor.author | 林鴻志 | en_US |
dc.contributor.author | 黃調元 | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.contributor.author | Huang, Tiao-Yuan | en_US |
dc.date.accessioned | 2014-12-12T01:55:05Z | - |
dc.date.available | 2014-12-12T01:55:05Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079911540 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/49087 | - |
dc.description.abstract | 在本篇論文中,我們利用I射線(I-line)光學步進機與雙重微影成像法來製作P通道多晶矽鰭式場效電晶體(FinFET)。這種新穎的雙重微影成像技術不僅能夠製作出鰭寬度(fin width)與閘極長度(gate length)小到80nm的多晶矽鰭式場效電晶體且有控制良好的關鍵尺寸,並在製程上有不錯的均勻性。我們也利用準分子雷射退火(excimer laser annealing)製程來提高多晶矽通道的品質。 所製作之鰭寬度80nm的鰭式場效電晶體具有陡峭的次臨界擺幅(subthreshold swing, 255mV/dec)、高的開關電流比(10^9)、與低的漏電流(<10^-14A),歸因於它較窄的鰭通道受到閘極良好的控制。另外,我們發現當元件的閘極長度等於或大於0.4μm時,晶界缺陷將顯著地影響次臨界擺幅;但是當閘極長度微縮至0.2μm或更小時,短通道效應(short channel effect)將主導次臨界擺幅的趨勢。 接著探討通道厚度50nm之低的高寬比(aspect ratio)元件。雖然低高寬比元件閘極的控制能力較差導致明顯的短通道效應;但是它們比通道厚度100nm之高的高寬比元件有較高的載子移動率與驅動電流,因其具有優良的準分子雷射退火結晶化條件。我們也探討了固相結晶法(solid phase crystallization)與準分子雷射退火兩者之鰭式場效電晶體的元件特性之差別。雖然固相結晶元件的電性比準分子雷射退火元件還差,但是它們電性的均勻性較準分子雷射退火元件為佳。 | zh_TW |
dc.description.abstract | In this thesis, we have developed a novel method which employs an I-line stepper and double patterning (DP) technique to fabricate p-channel poly-Si FinFETs for the first time. This novel DP technique is capable of not only generating fin widths (Wfin) and gate lengths (Lg) of poly-Si FinFETs down to 80nm with good critical dimension control, but also providing good process uniformity. We also use the excimer laser annealing (ELA) process to achieve high-quality poly-Si channels. The fabricated FinFETs with Wfin of 80nm have steep subthreshold swing (SS, 255mV/dec), high Ion/Ioff current ratio (10^9), and low leakage current (<10^-14A) owing to its narrow fin which enabls a better gate control over the channel. In addition, we found that the grain-boundary defects would predominantly affect the SS of devices when the Lg is equal to or larger than 0.4μm, but the short-channel effects (SCEs) dominate the trend of SS as devices are downscaled to Lg of 0.2μm and beyond. The low aspect ratio (AR) devices with channel thickness (TSi) of 50nm were also investigated and compared with devices with TSi of 100nm. Although the low AR devices have poorer gate controllability and exhibit obvious SCEs, they have higher mobility and drive current over the high AR devices with TSi of 100nm due to better crystallization results of ELA process. The differences in device characteristics between solid phase crystallization (SPC) and ELA FinFETs are also investigated. Although the SPC devices have poorer electrical characteristics than the ELA devices, they have better uniformity of electrical characteristics over the ELA devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 鰭式場效電晶體 | zh_TW |
dc.subject | 雙重微影成像法 | zh_TW |
dc.subject | 多晶矽 | zh_TW |
dc.subject | FinFETs | en_US |
dc.subject | Double Patterning Technique | en_US |
dc.subject | Polycrystalline Silicon | en_US |
dc.title | 利用雙重微影成像法製作多晶矽鰭式場效電晶體元件之特性研究 | zh_TW |
dc.title | A Study on the Device Characteristics of Polycrystalline Silicon FinFETs Fabricated with Double Patterning Technique | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |
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