使用新的量測方法探討三面閘極金氧半電晶體 氧化層隨機陷阱造成之擾動效應

Abstract

CMOS元件快速微縮的情況下，元件進入奈米世代以後，有相當多的挑戰必須克服，諸如短通道、效能的提升、閘極氧化層漏電流。截至目前，大部份挑戰皆是可以被克服的，諸如：使用極淺接面(ultra-thin junction)來克服短通道效應、strained Silicon來提昇元件性能。除此之外，通道中的載子濃度以及陷阱所在位置其結果會反映在元件特性的擾動上，例如驅動電流以及元件的臨界電壓上會產生擾動，導致元件特性不一致(mismatch)。

在此篇論文中，我們引用了一個新的機制，稱作隨機陷阱造成的擾動效應 Random Trap Fluctuation (RTF)，由於元件在長時間的操作下會產生相當多的隨機陷阱在通道表面，例如：閘級和汲極偏壓在汲極端所產生的熱載子(Hot Carrier stress)或利用加溫度產生熱載子(NBTI)對氧化層產生的缺陷，因此，此效應對於元件可靠度而言相當的重要，因為當元件被stress之後的陷阱是造成元件擾動的主要來源，但是以現在的量測技術而言，無法清楚的了解氧化層或是通道表面上的陷阱對是如何對電晶體的臨界電壓產生影響。在這篇論文中，我們提出一個新的量測方法稱為Random Trap Profiling (RTP) ，此方法可以找出通道中陷阱的分佈位置，利用本篇論文所提出的方法成功的解決差頻電荷幫浦法在面積太小的元件中無法量測的問題，因為元件尺寸在未來的元件趨勢中一定是越來越小，因此利用此方法即使元件面積很小也可以找出氧化層內缺陷的位置。

本文中，我們成功的使用新的方法來探討一批28奈米製程的三閘極電晶體，並成功的找出通道中陷阱的分佈位置，並且獲得幾項結論: (1) 我們成功的將通道中因為受到掺雜載子影響以及元件經過長時間操作後產生的陷阱對造成的影響分開。(2) 兩種不同的操作機制 (HC以及NBTI)分別操作在兩種不同類型的電晶體中(N型及P型)，對於N型來說，因為受到HC stress的影響，因此會在汲極端產生大量的陷阱，反觀P型元件，因為受到NBTI的影響，其產生的陷阱分佈是在通道中間。(3) 最重要的一點，我們利用此方法發現到無論是 HC stress 或者是 NBTI stress都會因為通道表面的不均勻(surface roughness effect)，或是因為上表面與側壁之間的角落效應(corner effect)而產生許多的陷阱，這是影響三維元件其可靠性的重要原因。

本文利用改良式萃取缺陷水平位置的方法，可以深入了解小尺寸元件缺陷位置，對於未來在研究新的CMOS元件可靠性以及性能上的優越表現可提供重要的設計參考指標。

As device channel length continues to scale beyond 100nm, we need to overcome many problems such as short channel effect, performance enhancement, and leakage current. So far, the major challenges have been overcome by difference technologies. For example, the short channel effect is solved by ultrathin junction depth and strained silicon device is used to enhance the electrical performance. While the variation properties induced by the discrete dopants and traps fluctuates the electronics properties significantly in the channel which lead to the mismatches of threshold voltage (Vth) and drive current.

In this thesis, we proposed a new mechanism, called Random Trap Fluctuation (RTF), which was considered to be another important issue for the devise after the long term stress. It varies with the devise after the stress, e.g., Hot Carrier Stress (HC) or Negative Bias Temperature Instability (NBTI). Also, it was observed that RTF is the major fluctuation source after the stress. But, the understanding of the real mechanisms and phenomena of oxide (or interface) traps induced Vth fluctuation has been very difficult and rare has been reported so far. In this thesis, we developed a newly technique, called Random Trap Profiling (RTP), to profile the stress-induced traps. Compared to the conventional lateral profiling technique of trap, Charge-pumping Profiling, RTP shows its advantages for applications to single and very small devices and very suitable for ultra-scaled 3D devices, such as FinFET or Trigate.

In this thesis, we used this new random trap profiling technique to identify the oxide trap position after the stress for a 28nm single-fin bulk trigate device and examine the physical mechanisms. As a consequence, several salient results can be drawn: (1) we successfully separated the fluctuation source from discrete dopant and the source from random traps after stress. (2) Two stress schemes, HC and NBTI, have been utilized to examine the trigate nMOS devices and trigate pMOS devices respectively. For trigate nMOS devices, the oxide traps are generated near the drain side after hot carrier (HC) stress; but for triage pMOS devices, they are generated more in the middle of the channel after NBTI stress. More importantly, (3) it has been found the reliability killer of advanced trigate devices should be the surface roughness on the side-wall and corner effect induced random traps either under the HC or NBTI stress, and the latter dominates the degradation of bulk trigate devices. These results will be helpful and valuable for the design of the next generation of bulk trigate CMOS devices beyond 20nm generation.