高介電係數金屬閘極平面式浮置閘極快閃記憶體特性及其微縮模擬

Abstract

在本篇論文中，我們建立了一個模擬方法來模擬高介電係數金屬閘極平面式浮置閘極快閃記憶體在寫入與消除的暫態行為，並使用 ＩＳＥ ＴＣＡＤ 模擬軟體來模擬不同通道長度下操作時的電場分佈。我們模擬有邊緣場效應與無邊緣場效應在通道長度為２０奈米的平面式浮置閘極快閃記憶體的寫入與消除操作下的比較，從我們模擬的結果可以得到邊緣場效應會造成我們在寫入與消除操作效率變差，因此在平面式浮置閘極微縮過程中，邊緣場效應扮演非常重要的角色。 為了在寫入與消除操作效率可以提高，我們必須改變其他高介電係數材料當作阻擋層並模擬在不同阻擋層材料的寫入操作特性，我們也改變閘極材料來模擬不同閘極材料在消除操作下的特性，由我們的模擬結果可以發現用氧化鑭（Ｌａ２Ｏ３）當作阻擋層可以有效地提高寫入與消除操作下的效率。

In this dissertation a simulation method to simulate the transient behavior of programming and erasing in high-k/metal gate planar floating gate flash memory is developed. We also simulate the electric field distribution under different channel length by ISE TCAD and compared the program/erase efficiency in channel length is 20 nm of planar floating gate flash memory with edge fringing field effect. From our simulation result, the program/erase efficiency will be degraded by edge fringing field effect. As a result, edge fringing field effect plays an important role in the scaling course of planar floating flash memory. To improve the program/erase efficiency, we have to simulate program characteristics and change other high-k materials as blocking layer. We also simulated erase characteristics under different gate material. From our simulation result, lanthanum oxide as blocking layer could effectively promote program/erase efficiency in planar FG.