三維垂直電阻式記憶體之開發

Abstract

在本研究中，將著重在以二氧化鉿薄膜以及非晶矽薄膜製作之垂直電阻式記憶體元件的電性分析與比較。實驗主要分為三部分，第一部分在於討論非晶矽薄膜製作之交錯式電阻式記憶體不同面積的電性比較。第二部分在於分析二氧化鉿薄膜以及非晶矽薄膜製作之垂直電阻式記憶體，而第三部分則是製作並分析雙層垂直電阻式記憶體。 從這三部分的實驗中，我們發現製作出之兩種垂直電阻式記憶體在連續操作之後都可以維持1個數量級以上的記憶窗口，且在25℃以及125℃的溫度下皆可以保持104秒。並觀察到雙層垂直電阻式記憶體上的兩個元件可以分別獨立操作且彼此不互相干擾。

In this thesis, the vertical structure with hafnium oxide and amorphous silicon resistive switching layers were prepared and studied. There are three main studies in this thesis. First, Ni/a-Si/n+ poly Si crossbar devices show a uniform set/reset voltage distribution due to corner effect. The second part is the results and discussion of vertical RRAM. In third part, we fabricate and analysis of the bilayer vertical RRAM. From the electrical measurements of vertical RRAM, we find that HRS/LRS ratio are stable over 1 order. Retention test showed that our samples could remain 104s without degradation at 25℃ and 125℃. In addition, the bilayer vertical RRAM cells are compatible with 2 bits operation.