可用於低電壓動態電壓與頻率調節系統之多相時脈設計與電壓準位轉換設計

Abstract

本論文提出一個可用於超低電壓動態電壓與頻率調節的系統。多個不同電壓準位電壓源是新興減少功耗的方法，此種方式需要電壓準位轉換器當作橋梁與不同電壓域溝通。所提出的跨接耦合的電壓轉換器表現較小的傳遞延遲、較低功耗以及最小的功耗與延遲乘積。由於利用了反效短通到的效應，對於溫度變化的抵抗力也提升許多。所提出的跨接耦合電壓準位轉換器是使用TSMC 65nm CMOS製成去設計出來的，在所有製程環境變數下都可以正確操作，並且輸入電壓從150mV 到1.0V都可以操作。 在動態電壓與頻率調節系統下，電壓準位轉換器可能會導致一些傳遞延遲與功耗增加。為了減少電壓轉換器所造成的影響，提出了一個對於製成、電壓、溫度強健的明確脈衝雙緣觸發的電壓準位轉換觸發器。它是由時脈脈衝產生器與差動串接電壓開關鎖存器組成。所提出的電壓準位轉換觸發器可以操作從近臨界電壓(0.4V)到超過臨界電壓(1.0V)，並且擁有負值的設置時間，如此一來，可以減少對時脈偏移與抖動的影響。 一個寬操作範圍的延遲鎖定迴路多相時脈被提出，在一個時脈週期裡擷取出八個相位，並且有兩個控制模式。第一個模式是逐次逼近控制，可以加速鎖定速度。第二個模式計數器模式，可以幫助監控對環境所造成的影響。此外，還有倍頻偵測器被提出可以防此倍頻的鎖定。為了使時脈產生器可以產生50% 負載週期，一個對製成、電壓、溫度強健及全數位操作的負載週期校正器被提出來。

This thesis proposes an ultra-low voltage (ULV) DVFS system. A multiple supply voltage is an emerging approach to reduce the power dissipation. The scheme requires a level converter as a bridge for different voltage domains. The proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance. The reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter may cause the propagation delays and power consumption in the DVFS system. In order to eliminate the overhead of level conversion, a PVT robust dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate latch (DCVSPG). The proposed LCFF can be operated from near-threshold region (0.4V) to super-threshold region (1.0V) and have a negative setup time to reduce the effect of the clock skew and jitter. A wide range DLL-based multiphase clocks is proposed. The eight phases is divided from a clock cycle. There are two control mode. The first mode is successive approximation register-controlled (SAR) mode which helps to accelerate the lock in speed. The second mode is counter mode to keep tracking the environmental effect. A harmonic detection is proposed to avoid a harmonic lock. To make the clock generator produce a 50% duty cycle clock signal, a PVT robust all-digital duty cycle corrector (DCC) is propose.