可用於低電壓系統超低功率電壓準位轉換器設計

Abstract

This thesis proposes a novel design of level shifter flip-flop cell for the applications in ultra-low voltage systems. In order to reduce a power dissipation, several approaches have been suggested and successfully implanted in modern designs. One of them is to divide system into clusters with multiple supply voltages. In order to successfully shift the voltages between those clusters, we need to insert the level shifters in between. However, the existing designs of the level shifters are consuming too much power and work only on super-threshold voltages so far. The level shifter in this proposed configurations are designed to meet the ultra-low voltages requirements of the modern circuit specifications and at the same time consume as little power as possible at the same time not causing too much delay for the signal. In order to solve above-mentioned problems (decrease the delay and power) the modified level shifter needs to be combined with the latch or flip-flop. The proposed level-converting flip-flop cell is composed of a clock pulse generator, a modified latch and a level shifter. The proposed LCFF can be operated from near-threshold region to super-threshold region and have a negative setup time to reduce the effect of the clock skew and jitter. The proposed level converter is designed using TSMC 65nm CMOS technology. It functions correctly across all process corners for a wide input voltage range.

This thesis proposes a novel design of level shifter flip-flop cell for the applications in ultra-low voltage systems. In order to reduce a power dissipation, several approaches have been suggested and successfully implanted in modern designs. One of them is to divide system into clusters with multiple supply voltages. In order to successfully shift the voltages between those clusters, we need to insert the level shifters in between. However, the existing designs of the level shifters are consuming too much power and work only on super-threshold voltages so far. The level shifter in this proposed configurations are designed to meet the ultra-low voltages requirements of the modern circuit specifications and at the same time consume as little power as possible at the same time not causing too much delay for the signal. In order to solve above-mentioned problems (decrease the delay and power) the modified level shifter needs to be combined with the latch or flip-flop. The proposed level-converting flip-flop cell is composed of a clock pulse generator, a modified latch and a level shifter. The proposed LCFF can be operated from near-threshold region to super-threshold region and have a negative setup time to reduce the effect of the clock skew and jitter. The proposed level converter is designed using TSMC 65nm CMOS technology. It functions correctly across all process corners for a wide input voltage range.