低溫多晶矽薄膜電晶體之高效能電壓移轉驅動電路研究

Abstract

在本篇論文中，我們以低溫複晶矽薄膜電晶體為基礎，提出了三種新電壓轉電路適用於主動式液晶顯示器及主動式有機發光顯示器。 為了設計電壓轉移電路，一開始我們先針對數種電壓轉移器包含了傳統式電壓轉移器使用HSPICE 做模擬並且探討電路架構、優缺點、效能…等等。從模擬的結果我們發現這些電路都有高功率消耗的特性存在，特別是傳統式的電壓移轉器。因此設計ㄧ個低功耗的電壓移轉器成為最初設計的出發點。我們提出了一電壓移電路-A目的是減少直流功率消耗。電路A是由一個P通道薄膜電晶體和二個N通到薄膜電晶體及一儲存電容所組成的，利用T3薄膜電晶體提供了回授路徑去抑制個電路的直流功率消耗。經由模擬及實際量測的結果發現所提出來的電壓移轉器-A的確在直流的功率消號上有明顯的減少。 運用低溫多晶矽薄膜電晶體實現系統整合在面板的技術會幾項重要的挑戰除了之前提到的功率消耗的問題及驅動能力的問題主要是因為低溫矽薄膜電晶體相較於金屬 氧化半導體場效電晶體有較高的臨界電壓及變異性，因此針對電路的驅動能力我們提出了電壓移轉器-B。電壓移轉器-B除了保有電壓移轉器-A之架構外，還多了ㄧ級輸入訊號的增強設計是由一組反向器所組成，經由模擬及量測的結果電壓移轉器-B 可將0到3.3 輸入電壓將輸出電壓平移到約 10 到 -10 電壓。 最後，因為先前提出來的電壓移轉器-A及電壓移轉器-B架構裡之儲存電容值(C1)約有0.0.1nF所以會有較大的Layout 尺寸。因為考量到面積的問題進而提出了電壓移轉器-C，電壓移轉器-C一樣是以電壓移轉器-A的架構來做延伸除了沒有儲存電容(C1)之外，還多了P通道薄膜電晶體(T4)及控制訊號(/IN)。由模擬及量測的結果得知電壓移轉器-C可以順利將0到5的輸入電壓提升到約10到-10輸出電壓。

In this thesis, three novel simple level shifter circuits using low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) for the integrated scan driver and scan driver of AMLCD and AMOLED has been proposed. For design the level shifter circuit, the power dissipation, output characteristics, advantage, disadvantage of several level shifter circuits is first studied by HSPICE circuit simulator. It is observed that high power consumption and low efficiency exist in the several level shifter circuits especially conventional level shifter circuit. First, the low power dissipation of system-on-panel (SOP) technology for LTPS TFTs is studied from the view point of circuit design. We proposed level shifter circuit_A to reduced direct current (DC) power dissipation. In proposed level shifter circuit_A composed of two n-type thin film transistors, one p-type thin film transistors, one storage capacitor and one control signal therefore, a level shifter circuit with simple circuit configuration is achieved, and furthermore to utilize n-type TFT (T3) apply for feed back voltage to gate of n-type TFT (T2) and then restrain direct current (DC) power consumption in level shifter circuit_A. Base on level shifter circuit_A skeleton, we also proposed level shifter circuit_B consideration of high efficiency that is mean low-amplitude voltage input signal to obtain high-amplitude voltage output signal. In proposed level shifter circuit_B in addition to circuit_A skeleton, has input setting bias compose of p-type TFT (T4) and n-type TFT (T5), input setting bias can help circuit_B use low input voltage to obtain high voltage amplitude, and then achieve high efficiency. Finally, we propose level shifter circuit_C consideration of small layout area, because in proposed circuit_A and circuit_B have storage capacitor (C1) about 0.01nF. Consequently, we use one more p-channel TFT (T4) and control signal (/IN) instead of storage capacitor (C1). Form propose level shifter circuit_C configuration, we can known the layout area size small than proposed circuit_A and circuit_B and also keep low power dissipation characteristics because base on proposed circuit_A except storage capacitor (C1).