應用於快閃記憶體之高面積效益混合域BCH解碼器

Abstract

隨著製程技術的提升，快閃記憶體的可靠度也隨之降低。因此錯誤更正碼被廣泛的應用以提高其可靠度。並且因為BCH碼適用於對抗隨機發生的錯誤，具有低硬體複雜度和低解碼延遲的特性，目前廣泛使用於記憶體系統的應用上。隨著記憶體的頁越來越大，BCH必須運算在更大的有限域中，造成硬體複雜度也隨之提高。本論文提出了兩種針對NOR和NAND快閃記憶體所設計的解碼器，並且利用混合域的演算法來降低硬體複雜度。 相較於傳統只能解單一錯誤的錯誤更正碼，本論文所提出的(274,256,2) BCH解碼器可以提高NOR快閃記憶體的可靠度。我們採用了簡單和高面積效益的step-by-step演算法，和全平行的架構以滿足低延遲的需求。此外，由於整個解碼器都運算在混合域中，因此不需要額外的硬體在不同的有限域中做轉換。根據UMC 90 nm的模擬結果，所提出的設計在2.5ns延遲下只需要23.2K邏輯閘數。 另一方面，我們提出了另一個針對NAND快閃記憶體所設計的(9200,8192,72) BCH編解碼器。相較於inversionless Berlekamp-Massey (iBM)的演算法，我們採用了Berlekamp-Massey (BM)演算法，並且使用了2級的混合域除法器。此外，利用錯誤位置多項式的每次疊代運算後項次最多只會增加1次的特性，提出了利用6個有限域乘法器的梯形排序架構。根據UMC 90 nm的post-layot模擬結果，所提出的設計需要147.8K邏輯閘數，在385MHz的操作頻率，其資料吞吐量可以達到3.08 Gb/s。 如此一來，我們所提出的設計可以適用於NOR和NAND快閃記憶體系統上以增加其可靠度。

With the processes aggressively scale down, the reliability of flash memories decrease significantly. To overcome this issue, error correcting codes (ECC) is widely used to enhance the reliability. Due to the advantage of powerful random-error-correcting capability, low complexity and low decoding latency, BCH codes are most well-known error control codes used in memory application. Moreover, as the page size of flash memory growing, BCH code computes over the large finite field, but the complexity overhead also increased.

In this thesis, we propose two works with composite field arithmetic for reducing complexity: one is for NOR flash memories, and the other one is for NAND flash memories. Compared with original single error correction methods, a (274,256,2) double error correcting BCH decoder is presented for NOR flash memories to improve the reliability. To meet the low latency requirement of NOR flash memory applications, fully-parallel architecture is implemented. Moreover, the step-by-step algorithm is applied due to its simplicity and high area-efficiency. Furthermore, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. The synthesis results base on UMC 90 nm CMOS technology show that the latency is only 2.5ns with 23.2K logic gates, which is suitable for NOR flash memory applications. On the other hand, a low-cost (9200,8192,72) BCH codec is also proposed for NAND flash memories. Instead of the common inversionless Berlekamp-Massey (iBM) algorithm, the Berlekamp-Massey (BM) algorithm using a low complexity 2-stage composite field divider is applied in key equation solver. Moreover, by making use of the fact that the degree of error location polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 90nm CMOS process, the proposed codec can achieve 385 MHz and 3.08 Gb/s throughput with 147.8K logic gates from post-layout simulation results. Therefore, our proposal can fully meet the criterion of flash memory systems to enhance the reliability of both NOR and NAND memories.