應用於高速記憶體系統之低複雜度全平行BCH編解碼器

Abstract

隨著記憶體製程的進步，記憶體越做越小，其可靠度也越來越低，被廣泛使用來改善儲存資料可靠度的錯誤更正碼的更正能力也隨之增加。本論文便是討論應用在高吞吐量系統中的高速記憶體所使用的錯誤更正碼，一般來說是BCH碼，其硬體架構的設計。此外，我們根據我們提出的架構，以應用在NOR快閃記憶體的錯誤更正碼為例，實作出晶片來驗證我們的想法。

為了符合高速記憶體系統的高速需求，錯誤更正碼會採用全平行架構來減少運算時間，但採用此架構卻會大量地增加硬體複雜度。然而我們發現到，在使用錯誤更正碼時，並不會同時使用編碼器與解碼器，所以我們提出了一種新的架構，讓編碼器和解碼器可以共享同一套硬體來減少電路複雜度。此外，我們也發現到解碼器主要是由常數乘法器所構成的，所以我們利用了矩陣觀念和BCH碼的特性，重新改寫錯誤位置多項式，並提出兩種解碼器架構，大量地減少解碼器所使用的常數乘法器。在 UMC 90nm 的製程下，我們所提出每256位元可更正兩位元錯誤的 BCH 編解碼器在 2.5 ns的運算時間下，第一種架構所需面積等效於14,789個XOR閘，第二種架構則是12,484個。

Latency-constrained memories are utilized for the high throughput systems. As the memory process is scaling down, error control codes are used to improve reliability. In the thesis, a double error correcting (DEC) BCH codec is designed for latency-constrained memory systems such as NOR flash memories. To meet the design target of latency-constrained memory systems, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Since the BCH encoder and decoder will not be activated simultaneously in NOR flash applications, we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, we developed two new expressions of error location polynomials based on matrix operations to reduce the number of constant finite filed multipliers (CFFMs) in Chien search, which dominates the hardware complexity of decoder. According to 90 nm CMOS technology, our proposed DEC BCH codec with 256-bit data length can achieve 2.5 ns latency with 14,789 gate count by using our first proposed method, whereas the second approach can achieve 2.5 ns latency with 12,484 gate count.