標題: 應用摺疊硬體架構實現畫面內畫面間預測之全域移動向量估測
Implementation of Intra/Inter Frame Predictive Global Motion Estimation with Folded Architecture
作者: 洪堂軒
Hong, Tang-Suan
董蘭榮
Dung, Lan-Rong
電信工程研究所
關鍵字: 全域移動向量估測;預測移動向量;折疊架構;global motion estimation;predictive motion vector;folded architecture
公開日期: 2011
摘要: 在影像處理或視訊處理中,全域移動向量是常被用來輔助處理的資訊。本篇論文中提出一個適用在高畫質影像的全域移動向量估測演算法,可應用在數位相機連拍全景影像的縫合上,在硬體實現方面,本篇論文也提出應用折疊技巧來降低面積成本的硬體架構。相較於過去一些文獻的研究需要計算所有區塊的移動向量,並且利用移動向量做數值分析估測出全域移動向量參數,本篇論文只等間隔取樣25個區塊來計算移動向量,以降低移動向量的運算成本且避免平坦區域和區域移動等干擾,並運用適合硬體實現的分群演算法得到全域移動向量。在移動向量估測中,利用預測移動向量來選擇適當的搜尋起始點以及適應性選擇搜尋範圍大小,以這上述兩種方法來降低運算量和確保移動向量的正確性。而演算法的驗證,則利用全域移動向量計算兩張影像重疊區域的PSNR值,本篇論文所提出的演算法和比較基準相比PSNR誤差可以達到0.5dB以下。在硬體架構方面,為了在達到即時處理的條件下降低面積成本,提出折疊處理單元陣列的硬體架構,重複利用處理單元陣列,實現高畫質影像的區塊匹配運算,最後整個硬體規格面積為192K gates,23K gates的晶片內記憶體,操作在100MHz,並且可以達到符合每秒處理30張影像的視訊處理標準。
Global motion estimation is widely used in image processing and video processing. This paper proposes a global motion estimation algorithm which can deal with the high-definition (HD) images. This algorithm can be used to do the stitching which is a popular application in digital camera. In hardware implementation, this thesis presents a folded architecture that can reduce hardware cost. Compared with the papers presented previously, they need many motion vectors to compute a global motion vector (GMV). This thesis chooses only 25 marcoblocks (MB) to calculate motion vectors and uses the clustering algorithm that can be implemented by hardware to compute global motion vectors. This thesis uses the predictive motion vectors (PMV) to choose an appropriate starting point and utilizes the adaptive search range to decrease the complexity of computation. Compared with benchmarks, the simulation results of this algorithm show that the two images’ overlapping region has PSNR errors below 0.5dB. To reduce the hardware cost and achieve the real time processing specification, this thesis uses folded architectures to implement HD image’s block- matching computation. We demonstrate a 2560-p,30-fps solution a 100MHz with 192k gate count and 23k gate count on chip memory.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079913626
http://hdl.handle.net/11536/49398
Appears in Collections:Thesis