表面形態及結晶條件對薄膜電晶體與非揮發性記憶體之影響

Abstract

近年來非揮發性記憶體的應用已遠超於任何人的想像, 像是個人電腦、邏輯運算幫手以及各式各樣的電子攜帶式產品。另一方面，為了成功實現系統整合面板(SOP)顯示器，提升LTPS-NVSM的品質當為首要任務。然而，在LTPS-NVSM中，仍舊缺乏探討通道結晶條件對於記憶體品質的影響的研究。基於此因，在本論文中我們將完整的探討表面形態以及結晶條件對於薄膜電晶體以及非揮發性記憶體之影響。 首先，我們使用熱氧化製程製備了不同的表面粗糙度，並且探討不同表面粗糙度對於寫入、抹除效率的影響。我們也發現了電晶體的電性(如載子遷移率、臨界電壓以及漏電流)與表面粗糙度有很強烈的相依性。此外我們發現通道厚度以及結晶溫度將會導致晶粒尺寸與缺陷密度的差異，也因此影響了電晶體與記憶體的電性。通道厚度較厚的元件提升了元件效能，卻導致較高的漏電流；而結晶溫度低的元件(580 °C)，拜能夠結晶出較大的晶粒所賜，展現了優越的電性。 另一方面，在本文中我們也探討了關於不同表面形態與結晶條件對於記憶體的各種種類之可靠度問題，包含了retention、閘極干擾(gate disturbance)以及汲極干擾(drain disturbance)。

Recently, the applications of the nonvolatile memory device have gone far beyond anyone else such as computer, personal digital assistant, and electronic portable equipment. On the other hand, to realize system-on-plane (SOP) display, the important task is to improve LTPS-NVSM. However, the impacts of the poly Si channel condition on NVSM are missing. As the result, this dissertation studies the impacts of morphology and crystallization condition on thin film transistors and nonvolatile memory. First, the roughness generated by thermal oxidation conditions was systematically reviewed for the nonvolatile memory P/E efficiency. Also, the mobility, threshold voltage, and leakage current exhibit a strong dependence on roughness. Moreover, we find the channel thickness and crystallization temperature altering the grain size and trap density, resulting in the different electrical characteristics of nonvolatile memory and transistors. Thicker channel devices enhance performance but case higher leakage current. On the other hand, lower SPC temperature (580 °C) devices show the better electrical characteristics, because their larger grain. On the other hand, we also study reliability issues such as retention, gate disturbance and drain disturbance with different morphology and crystallization condition.