H.264 視訊壓縮迴路濾波器之超大型積體電路設計

Abstract

以Block為單位的動態補償變換編碼之視訊編碼/解碼方法是目前最成功的視訊編碼技術。在低位元率的應用下，這種編碼/解碼的方式會產生blocking artifacts，讓畫面品質變差。即使能夠使用去塊濾波器去減少blocking artifacts，這種濾波器因為在運算上十分複雜，所以在處理器較弱的嵌入式編碼/解碼平台上對效能的影響很大。此篇論文目的在設計一個有效率的超大型積體電路去塊濾波器架構。 此外，在本研究中是先分析控制邏輯、計算單元和記憶器子系統，進行分來幫助有效率的設計整個硬體架構。本論文的迴路濾波器是以符合MPEG-4 AVC/H.264 [1]的演算法為目標。MPEG-4 AVC/H.264是一個新一代的視訊壓縮標準，它的視訊壓縮效率更優於MPEG-4 Advanced Simple Profile [2] 和H.263+。為這個標準，本論文設計了一個二階層的管線去塊濾波器和一個可以和AMBA[3] 匯流排架構界面溝通的codec加速器架構。管線的切法是以在特定目標晶片上能以 50 MHz 達到 CIF 解析度即時壓縮的目的來設計的。在本論文中提出的方法主要是在設計一個Real-time濾波器的硬體設計和整個匯流排系統架構，此外，我們使用一個SoC emulation Platform, ARM INTEGRATOR [4], 來驗證整個系統的功能性和量測整體的效能。

Block-based hybrid motion compensated transform video codecs are the most successful class of video coding technologies. For low bit-rate applications, this type of codecs suffer from blocking artifacts that causes an unpleasant visual effect. Even though deblocking filters can be used to smooth out blocking artifacts, it is quite often being omitted from low power embedded video terminals due to the computational complexity of a post processor. This thesis studies efficient VLSI architecture for deblocking filters for video applications. Thorough analysis on the complexity of control logic, computational units, and memory subsystem are conducted. In particular, an efficient implementation for the in-loop filter of the emerging new video coding standard, namely MPEG-4 AVC/H.264 [1] with superior performance compared to MPEG-4 Advanced Simple Profile [2] and H.263+, is presented. A two-stage pipeline deblocking hardware architecture and an generic codec accelerator infrastructure with an interface to AMBA bus protocol [3] is proposed. The feature of the proposed method is focused on an efficient hardware design for In-Loop Filter and the whole bus system architecture. Furthermore, to verify the functionality and performance of the proposed hardware design, an SoC emulation platform, the ARM INTEGRATOR[4], is used for H.264 hardware/software co-development.