半導體元件保護層蝕刻製程改善以降低聚合物殘留之研究

Abstract

為避免外在化學作用、環境中的水氣、污染物等與元件直接接觸而導致元件失效，半導體元件皆鍍有保護層以確保其可靠性，其中氮化矽（Si3N4）薄膜為最普遍之保護層。保護層蝕刻製程會衍生聚合物殘留（Polymer Residues）的問題，本論文研究提出三種方法改善此一殘留缺陷，進而提升晶圓廠內元件品質、可靠度及良率。 第一種方法是改良電漿灰化程式，加長灰化時間，加強對光阻與聚合物去除的效果；第二種方法是濕式清潔步驟（Wet Clean），利用超音波振盪產生氣泡去除附著於晶圓表面上的聚合物；第三種方法是改良保護層蝕刻條件，減少在蝕刻過程中所產生的聚合物。實驗分析結果顯示，調整蝕刻參數能有效減少聚合物殘留，且經由重複性驗證發現殘留數目明顯減少至10個以下。

The passivation layers of microchips inhibit the attacks from chemicals, moisture and contaminants to ensure reliable operation of electronic products. Silicon nitride (Si3N4) is the most common passivation material. This thesis studies the suppression of polymer residue generated by the passivation layer etch process. Three methods were proposed in order to reduce the polymer residues and enhance the device quality, reliability and yield. The first method improves the recipe of ashing process and extends the processing time to enhance the photoresist removal capability. The second is the post cleaning process by using the ultrasonic vibrations which generate small bubbles to remove the polymer residues on wafer surface. The third is to modify the etch process recipe to reduce the polymer drop during the wafer etching in chamber. Experimental results indicated the etch recipe modification may effectively reduce the polymer residue counts below 10.