淺溝槽隔離平坦化技術在奈米半導體積體電路製造製程研究

Abstract

伴隨著積體電路的進步到奈米等級製造技術，元件之間淺溝槽隔離面臨製造及技術整合問題，奈米尺寸之淺溝槽隔離可供應好的隔離效果及表面行為並防止漏電流。 淺溝槽隔離行為特性決定於氧化層化學汽相沉積及化學機械平坦技術。隨著積體電路元件尺寸縮小，伴隨而至在製造過程發生的微缺陷問題, 如: 氮化矽層無法有效停止化學機械研磨，而造成於研磨過程損傷矽基材，或是微細刮傷引起之元件漏電流。 本論文即針對化學機械研磨淺溝槽隔離製程，因研磨液效應引起之細微缺陷，包含矽基材損傷及微細刮傷。 透過高氧化層對氮化矽研磨速率選擇比，結合新淺溝槽隔離2-階段化學機械研磨流程，於積體電路製程製造可提供好的隔離效果及表面行為，進而控制並解決改善元件漏電流。

With semiconductor manufacture shrunk down to the nano-scale technology, the shallow trench isolation (STI) of the device would be faced to the nano-scale manufacturing and integration. The nano-scale shallow trench isolation could provide well isolation and surface condition to reduce current leakage. The well shallow trench isolation performance was dominated by the Oxide film deposition and following Chemical Mechanical Planarization (CMP). Accompanying device dimension shrunk down, the semiconductor manufacture micro defect issue, such as silicon substrate damage due to Nitride film not stopping the polishing planarization effectively, or device current leakage induced by micro scratch. This thesis would focus on the slurry effect on micro defect including silicon damage and micro scratch. Unique high SiO2/ Nitride removal rate selectivity slurry and combining new concept STI polishing sequence to two steps from three steps could purpose well isolation and surface condition. It also results in well device leakage performance on nano-scale semiconductor manufacture.