完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Li, Yiming | en_US |
dc.date.accessioned | 2014-12-08T15:06:38Z | - |
dc.date.available | 2014-12-08T15:06:38Z | - |
dc.date.issued | 2007-02-01 | en_US |
dc.identifier.issn | 0167-9317 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.mee.2006.02.010 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/5190 | - |
dc.description.abstract | We in this paper present an computational intelligence technique to extract semiconductor device model parameters. This solution methodology is based on a genetic algorithm (GA) with an exponential type weight function, renew operator, and adaptive sampling scheme. The proposed approach automatically extracts a set of complete parameters with respect to a specified compact model, such as a BSIM model for deep-submicron and nanoscale complementary metal-oxide-semiconductor (CMOS) devices. Compared with conventional artificial step-by-step fitting approaches, the proposed extraction methodology automatically tracks the shape variation of current-voltage (I-V) curves and examines the first derivative of I-V curves; therefore, highly accurate results can be obtained directly. Applying the renew operator will keep the evolutionary trend improving by removing the individuals without mainly features. The sampling strategy will speed up the evolution process and still maintain the extraction accuracy in a reasonable range. A developed prototype is successfully applied to extract model parameter of N- and P-metal-oxide-semiconductor field effect transistors (MOSFETs). This optimization method shows good physical accuracy and computational performance, and provides an alternative for optimal device modeling and circuit design in nanodevice era. Genetic algorithm based automatic model parameter extraction bridges the communities between circuit design and chip fabrication; in particular, it will significantly benefits design of system-on-a-chip. (c) 2006 Elsevier B.V. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | computational intelligence | en_US |
dc.subject | genetic algorithm | en_US |
dc.subject | extraction methodology | en_US |
dc.subject | computer-aided design | en_US |
dc.subject | compact model | en_US |
dc.subject | parameter quality | en_US |
dc.subject | CMOS devices | en_US |
dc.title | An automatic parameter extraction technique for advanced CMOS device modeling using genetic algorithm | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1016/j.mee.2006.02.010 | en_US |
dc.identifier.journal | MICROELECTRONIC ENGINEERING | en_US |
dc.citation.volume | 84 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 260 | en_US |
dc.citation.epage | 272 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000244383000009 | - |
顯示於類別: | 會議論文 |