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dc.contributor.authorLin, Yi-Nengen_US
dc.contributor.authorLin, Ying-Daren_US
dc.contributor.authorLai, Yuan-Chengen_US
dc.contributor.authorLin, Chuan-Hungen_US
dc.date.accessioned2014-12-08T15:06:41Z-
dc.date.available2014-12-08T15:06:41Z-
dc.date.issued2010-07-01en_US
dc.identifier.issn1607-9264en_US
dc.identifier.urihttp://hdl.handle.net/11536/5232-
dc.description.abstractNetworking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.en_US
dc.language.isoen_USen_US
dc.subjectVPNen_US
dc.subjectGatewayen_US
dc.subjectNetwork Processoren_US
dc.subjectBottlenecken_US
dc.subjectImplementationen_US
dc.titleVPN Gateways over Network Processors: Implementation and Evaluationen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF INTERNET TECHNOLOGYen_US
dc.citation.volume11en_US
dc.citation.issue4en_US
dc.citation.spage457en_US
dc.citation.epage463en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000280568400004-
dc.citation.woscount0-
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