标题: 以振荡信号测试超大型积体电路之串音障碍
VLSI Crosstalk Fault Testing with Oscillation Signals
作者: 吴明学
Ming-Shae Wu
李崇仁
Chung Len Lee
电子研究所
关键字: 串音障碍;震荡测试讯号;侵略线;受害线;测试图样产生;障碍模拟;内建式自我测试;方波测试讯号;周边扫瞄;交连线;路径延迟惯性;路径延迟;测试品质;Crosstalk Fault;Oscillation Test Signal;Aggressor Line;Victim Line;Test Pattern Generation;Fault Simulation;Built in Self Test;Squarewave Test Signal;Boundary Scan;Interconnect;Path Delay Inertia;Path Delay;Detection Quality
公开日期: 2005
摘要: 本论文就相关于震荡讯号的创新方法针对数位电路之串音障碍测试与内建自我测试技术的几个子题加以研究探讨。首先, 提出一个以基于震荡讯号测试串音障碍所引发的突波效应之测试方法,藉由采用一个震荡讯号源输入,以此使侵略性接线震荡,然后测试受害接线在两者之间存有串音障碍下所被引起的脉波效应。我们定义了一组符号和代数来运算讯号之传递及侦测。此方法简单且消除了传统方法在产生串音障碍测试图样时的复杂时间考量。在此研究中之测试图样产生器及障碍模拟器即是根据此测试方法所发展出来的。实验结果显示产生器流程可对此测试方法产生有效率的测试图样。
其次,我们提出一个以方波测试讯号,同样是检测串音障碍所引发之突波效应的自我测试方法。此方法运用于深次微米超大型积体电路之周边扫瞄测试环境,藉此来测试其内藏式电路的串音障碍。本测试方法利用提供一个测试方波,并结合乱数产生器,以此来引发并测试待测电路中因串音障碍所引起的短暂脉波。仅需对周边扫瞄电路单元加入简单的测试电路,即可进行本方法测试。实验结果显示利用本方法来测试一些大型的样本电路,可以很容易达到百分之九十以上的障碍涵盖率。
最后,我们提出一个利用路径延迟惯性原理,来测试系统电路连线之串音障碍的新测试方法。此方法无需使用时间上的量测,藉由在侵略性连线的输入端提供一个转换的讯号,以及在受害连线的输入端提供一个特定宽度的脉波─CWP,并且侦测此CWP脉波是否可以传输到受害连线的输出端,以此来测试是否有串音障碍存在。实验结果显示此方法在测试讯号无时间差及没有制程参数漂移的情况下有高的判别率。此方法仅简单,且在侦测连线上的串音障碍上有相当大的效率。
This dissertation studies several topics on testing and built-in self-testing of crosstalk faults of digital circuits with innovative methods which are related with oscillation signals. First, a test scheme for the induced-glitch type of the crosstalk fault by applying an oscillation signal on an aggressor line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines of the circuit under test (CUT). A set of symbols and associated algebra are defined to compute the propagation and detection of signals. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show that the described test generation procedure is effective in generating test patterns for this scheme.
Next, a BIST scheme based on a squarewave test signal to test also the induced-glitch type of the crosstalk fault of embedded circuits of SoC in the boundary scan environment for deep sub-micron VLSI is proposed. The scheme applies squarewave test signals in conjunction with pseudo random patterns to induce glitches which are caused by crosstalk faults and tests them. Modifications on boundary scan cells with simple added detection circuits to facilitate this test scheme are presented. Experimental results show that the average fault coverage obtained by applying the scheme to large size benchmark circuits can easily reach 90%.
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a pulse of specified width, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line to detect the existence of crosstalk faults. Experimental results show that the detection quality is high when no time skew at test signals and no process variation on interconnects occurs. The scheme is simple and is considered effective in detecting crosstalk faults.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008511822
http://hdl.handle.net/11536/52334
显示于类别:Thesis


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