以振盪信號測試超大型積體電路之串音障礙

Abstract

本論文就相關於震盪訊號的創新方法針對數位電路之串音障礙測試與內建自我測試技術的幾個子題加以研究探討。首先， 提出一個以基於震盪訊號測試串音障礙所引發的突波效應之測試方法，藉由採用一個震盪訊號源輸入，以此使侵略性接線震盪，然後測試受害接線在兩者之間存有串音障礙下所被引起的脈波效應。我們定義了一組符號和代數來運算訊號之傳遞及偵測。此方法簡單且消除了傳統方法在產生串音障礙測試圖樣時的複雜時間考量。在此研究中之測試圖樣產生器及障礙模擬器即是根據此測試方法所發展出來的。實驗結果顯示產生器流程可對此測試方法產生有效率的測試圖樣。 其次，我們提出一個以方波測試訊號，同樣是檢測串音障礙所引發之突波效應的自我測試方法。此方法運用於深次微米超大型積體電路之周邊掃瞄測試環境，藉此來測試其內藏式電路的串音障礙。本測試方法利用提供一個測試方波，並結合亂數產生器，以此來引發並測試待測電路中因串音障礙所引起的短暫脈波。僅需對周邊掃瞄電路單元加入簡單的測試電路，即可進行本方法測試。實驗結果顯示利用本方法來測試一些大型的樣本電路，可以很容易達到百分之九十以上的障礙涵蓋率。 最後，我們提出一個利用路徑延遲慣性原理，來測試系統電路連線之串音障礙的新測試方法。此方法無需使用時間上的量測，藉由在侵略性連線的輸入端提供一個轉換的訊號，以及在受害連線的輸入端提供一個特定寬度的脈波─CWP，並且偵測此CWP脈波是否可以傳輸到受害連線的輸出端，以此來測試是否有串音障礙存在。實驗結果顯示此方法在測試訊號無時間差及沒有製程參數漂移的情況下有高的判別率。此方法僅簡單，且在偵測連線上的串音障礙上有相當大的效率。

This dissertation studies several topics on testing and built-in self-testing of crosstalk faults of digital circuits with innovative methods which are related with oscillation signals. First, a test scheme for the induced-glitch type of the crosstalk fault by applying an oscillation signal on an aggressor line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines of the circuit under test (CUT). A set of symbols and associated algebra are defined to compute the propagation and detection of signals. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show that the described test generation procedure is effective in generating test patterns for this scheme. Next, a BIST scheme based on a squarewave test signal to test also the induced-glitch type of the crosstalk fault of embedded circuits of SoC in the boundary scan environment for deep sub-micron VLSI is proposed. The scheme applies squarewave test signals in conjunction with pseudo random patterns to induce glitches which are caused by crosstalk faults and tests them. Modifications on boundary scan cells with simple added detection circuits to facilitate this test scheme are presented. Experimental results show that the average fault coverage obtained by applying the scheme to large size benchmark circuits can easily reach 90%. Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a pulse of specified width, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line to detect the existence of crosstalk faults. Experimental results show that the detection quality is high when no time skew at test signals and no process variation on interconnects occurs. The scheme is simple and is considered effective in detecting crosstalk faults.