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dc.contributor.authorChen, Shih-Hungen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:06:46Z-
dc.date.available2014-12-08T15:06:46Z-
dc.date.issued2010-06-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2010.01.030en_US
dc.identifier.urihttp://hdl.handle.net/11536/5308-
dc.description.abstractNMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector. (C) 2010 Elsevier Ltd All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleInvestigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.microrel.2010.01.030en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume50en_US
dc.citation.issue6en_US
dc.citation.spage821en_US
dc.citation.epage830en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000278644400011-
dc.citation.woscount1-
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