適合超大型積體電路設計的高速傅立葉轉換系統架構

Abstract

在本篇論文中，我們設計多套快速傅立葉轉換器架構以應用於日趨重要的即時信號處理系統上。它們具有規則性，單元性，且有管線並行處理的功能以提高運算速度，這些都是超大型積體電路的架構所必需具備的基本特性。 首先，我們利用傅立葉轉換的矩陣表示法來設計架構，而沒有利用到現有的快速演算法，因此它們保持了架構的規則性及區域性，同時可大大提高整個系統的運算速度。 另一種架構型式是根據最近提出的兩種傅立葉轉換的快速演算法，叫巢狀式溫諾格雷演算法和質數演算法來設計，它們僅需要很少的硬體設備就可執行大長度的傅立葉轉換，同時也具有令人滿意的運算速度。 最後，我們比較本篇論文所提出的一些架構，並作一結論。

In this thesis, some high speed architectures for DFT computation are proposed which are suitable for VLSI system implementation. One type of DFT architectures are based on matrix representation of DFT and no fast Fourier transform algorithm is used. These architectures are derived from the concept of systolic array processors. They are regular, modular and pipelinable which are the basic requirements of VLSI system. The whole system throughput rate can achieve the pipeline rate of the composing arithmetic cells in the architecture. The other type of DFT architectures are realized using recently developed Winograd Fourier transform algorithm and prime factor algorithm. They require much less hardware than conventional FFT structures to compute a long length DFT and at the same time maintain satisfactory time performance. The comparison of some DFT architectures are made based on the criterions of hardware complexity, latency and throughput.