超大型積體組合電路自動測試圖樣產生系統

Abstract

本篇論文對超大型積體組合電路，研製一個很有效率的自動測試圖樣產生系統。這個系統有三個可供使用者選擇的測試圖樣產生器，用來自動產生測試圖樣，而且使用一個很有效率的故障模擬汽來評估故障涵蓋率(Fault Coverage)。三個測試圖樣產生器分別是：一個使用線性迴授移位暫存器(LFSR)所做成的隨機圖樣產生器，一個虛隨機圖樣產生器(DISRUPT)，一個改良的具有動態壓(Dynamic Compacton)能力的決定性測試圖樣產生器(SLOPE1)。藉著和故障模擬器緊密的結合，這個系統比以前所發表過的系統產生較短的測試圖樣長度，達到更高的故障涵蓋率。

In this thesis, an automatic test pattern generation(ATPG) system forVLSI combinational circuits is presented. The presented ATPG system has three optional test pattern generators to generate tests and a fault simulation-ACCEPT to evaluate the fault coverage. The three test pattern generators include a random pattern generator with the linear feedback shift register(LFSR) technique, a pseudo-random pattern generator-DISRUPT, and a modified deterministic test pattern generator- SLOPE1 which, employs the dynamic compaction capability to increase the faul coverage. The LFSR generator and DISRUPT can be combined to use and they constitute a highly effective pseudo-random test generation procedure. The generators, incorporated with ACCEPT, make the ATPG system generate test sets much smaller than those reported by other published ATG systems while still achieving the same or better fault coverage with comparable system run times. The ATPG system is implemented in C language on a SUN 3/280. workstation under UNIX operating system.