準分子雷射低溫製備之鈦酸鍶鉛薄膜元件特性分析之研究

Abstract

本論文將研究以先進低溫製程技術製備之鈦酸鍶鉛((Pb,Sr)TiO3, PbSrT)薄膜之電容特性，採用的低溫製程技術包含先進低熱預算退火製程及低溫沉積製程等。本研究中，Pt/PSrT/Pt與Pt/PSrT/Si多層膜結構分別被應用於模擬capacitor over bit line (COB)結構及鐵電閘場效電晶體中的 金屬/鐵電/半導(metal/ferroelectric/semiconductor, MFS)結構。 以雷射剝鍍法(PLD)在低溫(200 oC)所沉積的鈦酸鍶鉛薄膜為非結晶態，具有極差的鐵電特性，因此需要後續處理以改善電氣特性。傳統的快速退火製程(RTA)可輕易增進鈦酸鍶鉛薄膜的結晶性，但同時亦因表面缺陷(如：微孔洞)及界面擴算導致急遽惡化的漏電流。準分子雷射退火(ELA)可在局部區域達到高溫而不損傷下層結構，因此可用於增進鈦酸鍶鉛薄膜的結晶性。鈦酸鍶鉛薄膜經由準分子雷射退火後，可減少薄膜表面氧缺乏，並在薄膜上層區域有較佳的結晶性。然而，準分子雷射退火之效用僅作用於薄膜表層形成”淺層加熱”，無法使整層薄膜都能結晶。而以準分子雷射退火使鈦酸鍶鉛薄膜進行預先產生晶核，然後搭配快速退火製程促使晶粒成長的二階段雷射輔助退火製程則能同時實現緻密的薄膜表面、良好的結晶性、可區別的電容–電場(C-E)電滯曲線、較大的介電常數(492)及壓抑的漏電流。因而，此二階段雷射輔助退火製程能成功製備具有優越的鐵電特性、較高的崩潰電壓、較長的元件壽命之Pt/PSrT/Pt電容器。 以雷射剝鍍在低基板溫度(300 – 450 oC)所製備的鈦酸鍶鉛薄膜具有緻密的薄膜表面、顯著的結晶性及明顯的鐵電特性。適當的沉積溫度有助於減少鈦酸鍶鉛薄膜的界面能態及陷阱能態，及較小的漏電流，其電流分析顯示Pt/PSrT/Pt電容在低電場時的導電機制主要為Schottky emission (SE)，在高電場則由Poole–Frenkel emission (PFE)主導，在本文中將以能帶圖分析探討此導電機制。實驗顯示，以雷射剝鍍製備的鈦酸鍶鉛薄膜，其從優取向結晶結構及陷阱能態隨著基板溫度而變化，進而影響薄膜電氣特性。因此，鈦酸鍶鉛薄膜的介電常數及鐵電特性亦深受從優取向影響，所以在350 – 400 oC沉積的鈦酸鍶鉛薄膜顯現強化的(100)從優取向結晶性與最佳化的鐵電特性。疲勞操作測試顯示當鈦酸鍶鉛薄膜的沉積溫度高於350 oC時，Pt/PSrT/Pt電容經1010次切換操作後，僅損失低於17%的殘留極化值。本文中，400 oC製備的鈦酸鍶鉛薄膜顯示強化的結晶性及較少的缺陷，因此具有最低的漏電流、最佳的崩潰特性，即使經過1010次切換操作後亦顯現近乎無疲勞的的電流密度–電場特性。 更進一步分析指出，雷射剝鍍低溫製備的鈦酸鍶鉛薄膜其電流密度隨著量測溫度及外加電場增加而增加。當量測溫度低於150 oC時，鈦酸鍶鉛薄膜可測得穩定的電流密度及薄膜電阻，換言之，鈦酸鍶鉛薄膜在積體電路元件操作溫度範圍內具有相當穩定性，可適用於記憶體應用。而當量測溫度為100 – 390 oC，鈦酸鍶鉛薄膜亦顯現出強烈的負溫度–電阻係數(negative temperature coefficient of resistance, NTCR)特性，此大範圍的薄膜阻值變動，暗示鈦酸鍶鉛薄膜可應用於熱敏電阻領域。 此外，鈦酸鍶鉛薄膜的從優取向結晶性、微結構以及電氣特性亦可經由調整雷射剝鍍時氧氣氛壓力參數(50 – 200 mTorr)而改變。當氧氣氛壓力高於100 mTorr時，鈦酸鍶鉛薄膜將從(100)從優取向結晶性轉換成(110)從優取向結晶性。因此，順電/鐵電轉變及薄膜介電常數亦與從優取向結晶性及氧含量相關而受到氧氣氛壓力調變之影響。較高的氧氣氛壓力有助於減少鈦酸鍶鉛薄膜中的氧空缺，使鈦酸鍶鉛薄膜具有較小的漏電流、較高的崩潰電場，進而增加Pt/PSrT/Pt電容器的元件壽命。電流分析顯示Pt/PSrT/Pt電容在低電場時的導電機制主要為Schottky emission，在高電場則由Poole–Frenkel emission主導，但氧氣氛壓力為200 mTorr時，在低/高電場下都將僅由Schottky emission主導。藉由能帶圖分析疲勞特性，可得知在較低氧氣氛壓力製備的鈦酸鍶鉛薄膜其疲勞特性深受介面能態影響，相對的，在較高氧氣氛壓力製備的鈦酸鍶鉛薄膜其疲勞特性則由深的陷阱能態主導，這種差異導因於氧空缺集中在介面或薄膜內。 鈦酸鍶鉛薄膜亦可以雷射剝鍍法低溫(300 – 450 oC)沉積在p型矽晶片上應用於 金屬/鐵電/半導 結構。實驗結果顯示基板溫度可強烈增進鈦酸鍶鉛薄膜結晶性及影響其電氣特性，並且在此沉積溫度範圍內亦無發現交互擴散現象存在 鐵電/半導 (PSrT/Si)介面。300 oC沉積之鈦酸鍶鉛薄膜內將存在負的陷阱電荷，因此顯現出小的且為逆時針方向的介電場數–電場電滯曲線及正偏移的平帶電壓(flatband voltage)。隨基板溫度增加，鈦酸鍶鉛薄膜的結晶性顯著改善，因此具有較小的漏電流、較少的陷阱能態在電極界面、順時針方向的介電場數–電場( -E)電滯曲線及較大的記憶窗(memory window)。然而，過高的基板溫度(450 oC)可能導致較嚴重的的氧化鉛(Pb-O)揮發，產生較多的缺陷及漏電流特性惡化。分析固定電荷密度(fixed charge density)及平帶電壓偏移，顯示其陷阱能態特性亦與電氣特性相契合。本研究中，即使經過1010次切換操作後僅導致記憶窗極小的變動(< 11%)，因此可實現良好的耐疲勞特性。總結，透過準分子雷射退火及沉積技術之整合，可在低溫製備具有良好結晶性、優越電氣特性之鈦酸鍶鉛(PSrT)薄膜電容元件，進一步與積體電路技術整合後，將成為深具潛力的非揮發性記憶元件。

The characteristics of (Pb,Sr)TiO3 (PSrT) films prepared by novel low-temperature techniques, including low-thermal budget annealings and a low temperature deposition, are systematically investigated in this dissertation. The multilayered structures of Pt/PSrT/Pt and Pt/PSrT/Si are proposed to simulate the practical capacitor over a bit-line (COB) and metal/ferroelectric/semiconductor (MFS) configuration of ferroelectric gate FET, respectively. PSrT films pulsed-laser deposited at 200 oC exhibits amorphous crystallinity and worse ferroelectricities, which indeed require a post-treatment to reform electrical properties. Conventional rapid thermal annealing (RTA) can evidently improve the crystallinity of PSrT films but seriously degrade leakage current due to the unwilling surface defects (i.e. pin holes) and interfacial diffusion. An excimer laser annealing (ELA) technique can recognize local-high-temperature heating within short duration without the underlying damage, proposed to enhance the crystallinity of films. After ELA, the decrease of oxygen deficiency and superior crystallinity of the upper region of films can be obtained. However, the effect of ELA is very limited and can’t crystallize the whole thickness of film. Furthermore, the novel laser-assisted two-step process, the combination of initial crystal seed induced by ELA and the grain growth carried out by subsequent RTA, which can realize the dense surface, well crystallinity, distinct C-E hysteresis loops, large dielectric constant of 492, and inhibited leakage current density all at once. Thus, the superior ferroelectricity, higher breakdown field and longer lifetime of Pt/PSrT/Pt capacitors can be successfully achieved by this laser-assisted two-step process. PLD PSrT films prepared at low substrate temperatures (Ts), ranging from 300 to 450 oC, behave dense surface, evident crystallinity, and apparent ferroelectric properties. Films grown at appropriate Ts yield fewer interface states and fewer trapping states, leading to a smaller leakage current. The conduction mechanism is identified as Schottky emission (SE) at low electric fields and as Poole–Frenkel emission (PFE) at high electric fields. The mechanism analysis shows the electrical characteristics strongly rely on the preferred-oriented textures and trapping states, adjusted by the low substrate temperature (Ts ≤ 450 oC) during PLD process. In addition, the dielectric constant and ferroelectricity are associated with the preferred orientation. The enhanced (100) preferred orientation of films deposited at Ts = 350 – 400 oC exhibits optimum ferroelectricity. The loss in remnant polarization and coercive field is found to be less than 17 % after 1010 switching cycles when Ts is higher than 350 oC. Consequently, the 400 oC-deposited PSrT film reveals the lowest leakage current, nearly fatigued-free J-E characteristics after 1010 switching cycles, and the best breakdown property, attributed to the enhanced crystallinity and fewer defects. Moreover, the current density of these low-temperature PLD PSrT films increases as the measurement temperature and applied fields increase. Films show high stability of leakage current and film resistance below 150 oC, which is important and well for memory application during the operation temperature of IC. Films exhibit strong negative temperature coefficient of resistance (NTCR) behavior at temperatures ranging of 100 – 390 oC. The larger resistance range of the PLD PSrT films infers a potential application of thermistor sensor. Besides, the preferred orientation, microstructure, and electrical characteristics of PLD PSrT films could be apparently affected by ambient oxygen pressures (PO2), ranging from 50 to 200 mTorr. Films exhibit (100) preferred orientation at lower PO2 and then transit to (110) preferred orientation above 100 mTorr. The paraelectricity/ferroelectricity transition and dielectric constant of films are associated with the preferred orientation and oxygen concentration at various PO2. Films deposited at higher PO2 exhibit the longer lifetime, higher breakdown field and smaller leakage current density as a consequence of fewer oxygen vacancies (OVs). Except for the case of films deposited at 200 mTorr, the conduction mechanism is identified as SE/PFE at low/high electric fields. The fatigue properties are dominated by interfacial states at low PO2 and by deep trapping states at high PO2, which could be ascribed to OVs located at the interfaces and inside PSrT films, respectively. PLD PSrT films on p-type Si were studied at low Ts (300 – 450 oC) for MFS applications. The Ts strongly enhances film crystallinity without significant inter-diffusion at the PSrT/Si interface and affects the electrical properties. As Ts increases, films have smaller leakage currents, fewer trap states at the electrode interfaces, clockwise -E hysteresis loops, and larger memory windows correlated with superior crystallinity. Conversely, 300 oC-deposited films exhibit the small and counterclockwise loop with positive shift of the flatband voltage, attributed to more negative trap charges within the films. However, the high Ts (450 oC) may produce serious Pb-O volatilization, incurring more defects and leakage degradation. The analyses of fixed charge density and flatband voltage shift reveal the trap status and agree well with the leakage characteristic. The excellent fatigue endurance with small variation of memory windows (< 11%) after 1010 switching is also demonstrated. Concisely, PSrT films can be the most promising candidate for future NVRAM capacitor, since the low-temperature process can be compatible to the IC’s integration.