互補式金氧半邏輯閘輿連接網之物理性延遲模式及其在最佳化輿自動設計上之應用

Abstract

本論文之目的有三，一為建立不具連接網互補式金氧半及－或－反閘 (或-及-反閘) 之通用性延遲模式, 二為建立具連接網互補式金氧半反閘之物理性延遲模式與功率消 耗模式，三為將這些延遲與功率消耗模式應用在最佳化與自動設計上，以便尋找出設 計準則與性能改進方法。 在建立不具連接網互補式金氧半及-或-反閘 (或-及-反閘) 之通用性延遲模式中, 首 先根據電晶體在上升/下降時間的工作區間, 建立互補式金氧半及-或-反閘(或-及-反 閘) 的大訊號等效電路, 並且把該大訊號等效電路線性化, 其次以零值時間常數之法 則, 求出主極點, 最後以主極點為變數, 寫出輸出波形方程式。對於各種不同組態、 尺寸、電容負載、元件參數、及輸入訊號，計算延遲模式的運算結果與SPICE 的模擬 結果所產生之相對誤差, 發現最大相對誤差均小於 30%, 並且對於常用的元件尺寸, 最大相對誤差將更小。此外，可針對特殊的應用範疇，而將最大相對誤差調整得更小 。 在建立具連接網互補式金氧半反閘之物理性延遲模式中，由於電晶體在上升/ 下降時 間內, 係工作在線性與飽和兩區間內，且零點的效應亦不得忽視，是故以修飾的主極 點主零點方法，求出各工作區間的等效主極點，然后再以這些等效主極點為變數，寫 出輸入波形方程式。在各式各樣條件下，此等延遲模式所產生的最大相對誤差均小於 15%。 由於具連接網與具純電容負載互補式金氧半反閘之輸出波形不同，是故在這兩種情況 中總功率消耗應不相同；但當輸入訊號不與特征波形相距甚遠時，短路功率消耗可忽 略不計，此時具連接網的總功率消耗與具純電容負載者相同。在各種情況下，此功率 消耗模式所產生的最大相對誤差均小於12%。 將發展完成的延遲與功率消耗模式佐以最佳化數學方法，則可建立一套電腦輔助自動 化設計程式，這個程式可根據輸入的邏輯閘尺寸、連接網組態、連接網電阻電容值、 及性能改進方法，而決定出具最佳化性能的驅動器/ 轉發器之大小與個數；或者，根 據給定的總功率消耗，而求得具最佳化性能的驅動器/ 轉發器之大小與個數。由於這 個程式所需要的電腦時間與記憶體容量都遠小於 SPICE，因此，這個程式在未來的超 大型積體電路自動設計中, 具備高度的發展潛力。

Efficient physical timing models for complex CMOS AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS/AOI/OAI gates with wide rages of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% for the gates with commonly used device dimensions. From the timing models of CMOS AOI/OAI gates, the rules to determine the worst-case timing condition of a AOI/OAI gate and the guideline to determine th optimal gate configuration have also been explored. The developed timing models and design rules/guidelines are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a ggood accuracy and a reasonable CPU-time consumption. Reasonable accuracy, wide applicable ranges, high computation efficiency, and ability in speed optimization and autosizing make the developed timing models quite attractive in MOS VLSI/ULSI timing verification. Physical delay models and power dissipation models for small-geometry CMOS inverters with RC line and tree intercomections are presented. Through extensive comparisons with SPICE simulation results, it is shown that th maximum relative error in delay-time calculations is 15% and in power-dissipation calculations is 12% for 1.5 um CMOS inverters with RC line and tree interconnections. Moreover, the models have wide applicable ranges of circuits and device parameters. Based upon the mathematic optimization method as well as the developed power dissipation models and the delay models of CMOS inverters with RC line and tree interconnections, an experimental sizing program is constructed for improving various circuit performances like delay time, power-delay product, and delay time subject to constraint on power dissipation. In this CAD program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for optimal circuit performance. The four performance improvement techniques use minimun-size repeaters, optimal-size repeaters, cascaded input drivers, and optimal-size repeaters with cascaded input drivers to obtain the optimal circuit performance. It is found from the sizing results of the experimental program that the required tapering factor for minimum power-delay product in cascaded input drivers of interconnection lines and trees is in the range of 2-6 and in the range of 4-8 for a minimum delay. MOreover, adding a small number of drivers/repeaters with large sizes is more efficient in obtaining the optimal circuit performance. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay time and power-delay product. By applying the augmented Lagrange method, the experimental sizing program can optimize the delay time subject to constraint on power dissipation. The ability to optimize the delay time with power dissipation constratint makes the experimental sizing program more practical and versatile in improving the performace of CMOS logic gates with RC line and tree interconnections.