标题: | 互补式金氧半逻辑闸舆连接网之物理性延迟模式及其在最佳化舆自动设计上之应用 |
作者: | 萧明椿 XIAO,MING-CHUN 吴重雨 WU,CHONG-YU 电子研究所 |
关键字: | 积体电路;电晶体;互补式金氧半逻辑;连接网;延迟模式;互补式金氧半反闸;SPICE |
公开日期: | 1989 |
摘要: | 本论文之目的有三,一为建立不具连接网互补式金氧半及-或-反闸 (或-及-反闸) 之通用性延迟模式, 二为建立具连接网互补式金氧半反闸之物理性延迟模式与功率消 耗模式,三为将这些延迟与功率消耗模式应用在最佳化与自动设计上,以便寻找出设 计准则与性能改进方法。 在建立不具连接网互补式金氧半及-或-反闸 (或-及-反闸) 之通用性延迟模式中, 首 先根据电晶体在上升/下降时间的工作区间, 建立互补式金氧半及-或-反闸(或-及-反 闸) 的大讯号等效电路, 并且把该大讯号等效电路线性化, 其次以零值时间常数之法 则, 求出主极点, 最后以主极点为变数, 写出输出波形方程式。对于各种不同组态、 尺寸、电容负载、元件参数、及输入讯号,计算延迟模式的运算结果与SPICE 的模拟 结果所产生之相对误差, 发现最大相对误差均小于 30%, 并且对于常用的元件尺寸, 最大相对误差将更小。此外,可针对特殊的应用范畴,而将最大相对误差调整得更小 。 在建立具连接网互补式金氧半反闸之物理性延迟模式中,由于电晶体在上升/ 下降时 间内, 系工作在线性与饱和两区间内,且零点的效应亦不得忽视,是故以修饰的主极 点主零点方法,求出各工作区间的等效主极点,然后再以这些等效主极点为变数,写 出输入波形方程式。在各式各样条件下,此等延迟模式所产生的最大相对误差均小于 15%。 由于具连接网与具纯电容负载互补式金氧半反闸之输出波形不同,是故在这两种情况 中总功率消耗应不相同;但当输入讯号不与特征波形相距甚远时,短路功率消耗可忽 略不计,此时具连接网的总功率消耗与具纯电容负载者相同。在各种情况下,此功率 消耗模式所产生的最大相对误差均小于12%。 将发展完成的延迟与功率消耗模式佐以最佳化数学方法,则可建立一套电脑辅助自动 化设计程式,这个程式可根据输入的逻辑闸尺寸、连接网组态、连接网电阻电容值、 及性能改进方法,而决定出具最佳化性能的驱动器/ 转发器之大小与个数;或者,根 据给定的总功率消耗,而求得具最佳化性能的驱动器/ 转发器之大小与个数。由于这 个程式所需要的电脑时间与记忆体容量都远小于 SPICE,因此,这个程式在未来的超 大型积体电路自动设计中, 具备高度的发展潜力。 Efficient physical timing models for complex CMOS AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS/AOI/OAI gates with wide rages of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% for the gates with commonly used device dimensions. From the timing models of CMOS AOI/OAI gates, the rules to determine the worst-case timing condition of a AOI/OAI gate and the guideline to determine th optimal gate configuration have also been explored. The developed timing models and design rules/guidelines are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a ggood accuracy and a reasonable CPU-time consumption. Reasonable accuracy, wide applicable ranges, high computation efficiency, and ability in speed optimization and autosizing make the developed timing models quite attractive in MOS VLSI/ULSI timing verification. Physical delay models and power dissipation models for small-geometry CMOS inverters with RC line and tree intercomections are presented. Through extensive comparisons with SPICE simulation results, it is shown that th maximum relative error in delay-time calculations is 15% and in power-dissipation calculations is 12% for 1.5 um CMOS inverters with RC line and tree interconnections. Moreover, the models have wide applicable ranges of circuits and device parameters. Based upon the mathematic optimization method as well as the developed power dissipation models and the delay models of CMOS inverters with RC line and tree interconnections, an experimental sizing program is constructed for improving various circuit performances like delay time, power-delay product, and delay time subject to constraint on power dissipation. In this CAD program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for optimal circuit performance. The four performance improvement techniques use minimun-size repeaters, optimal-size repeaters, cascaded input drivers, and optimal-size repeaters with cascaded input drivers to obtain the optimal circuit performance. It is found from the sizing results of the experimental program that the required tapering factor for minimum power-delay product in cascaded input drivers of interconnection lines and trees is in the range of 2-6 and in the range of 4-8 for a minimum delay. MOreover, adding a small number of drivers/repeaters with large sizes is more efficient in obtaining the optimal circuit performance. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay time and power-delay product. By applying the augmented Lagrange method, the experimental sizing program can optimize the delay time subject to constraint on power dissipation. The ability to optimize the delay time with power dissipation constratint makes the experimental sizing program more practical and versatile in improving the performace of CMOS logic gates with RC line and tree interconnections. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT782428003 http://hdl.handle.net/11536/54578 |
显示于类别: | Thesis |