傳統及淺摻雜洩極金氧半場效電晶體之共通模式- 臨界電壓、洩極電流、基片電流及電體電荷

Abstract

本論文提出能使用在傳統及淺摻洩極金氧半場效電晶體之共通模式，此共通模式包括 臨界電壓、洩極電流、基片電流及電晶體電荷。傳統結構的金氧半場效電晶體在比例 縮小後有嚴重的高電場效應，利用淺摻雜結構可改善此一缺點，但會產生額外的壓控 寄生電阻。本論文所用的測試鍵乃由工業技術研究院電子工業研究所提供，此測試鍵 包括傳統及淺摻雜洩極兩種結構。在臨界電壓的模式中，我們使用電荷分配及空乏電 荷重疊的原理，並把通道離子佈植用台階分佈來模擬。考慮台階接面的內在電位，具 有連續性的臨界電壓即可導出，將源(洩)極的高摻雜濃度改為淺摻雜濃度，則淺摻洩 極結構的臨界電壓亦可算出。在洩極電流的模式中，考慮場控移動率，短通道臨界電 壓，定值寄生電阻，並把淺摻雜區域視為埋藏通道金氧半場效電晶體，此外利用一次 元近似法，則工作於線性及飲和區的洩極電流即可推導出，此洩極電流模式包括傳統 及淺摻雜洩極結構。在基片電流模式中，利用虛二次元近似法可得到在通道及洩極之 通道長度調變因子和最大電場，利用一簡化之基片電流公式和所推導出的洩極電流， 則可算出傳統及淺摻雜洩極金氧半場效電晶體的基片電流，此外我們利用二次元數值 模擬來探討淺摻雜洩極結構的雙峰特性。在電荷模式中，我們定義一個新的參數使得 內在電荷在經過線性和飽和區時能平滑的連接，利用三個埋藏通道元件來模擬淺摻雜 區域，則可導出外在電荷模式，此外在電荷模式亦能用於重摻雜區域。以上所有模式 的參數皆能粹取出來，使用粹取之參數所計算之結果和實驗值相比較皆能令人滿意的 相荷。本論文最後描述其貢獻和未來研究之方向。

In this thesis, the analytic common models for the threshold voltage, the drain current, the substrate current, and the transistor charges of both conventional and LDD MOSFET's have been developed. In chapter 1, we will point out the fact that the LDD structure can reduce the high7 field effects existing in conventional. MOSFET's but the extra parasitic resistance in the LDD structure, which is bias7 controlled, will reduce the transconductance and increase the saturation voltage. A set of test devices with conventional and LDD structures fabricated by ERSO, ITRI, have been measured and characterized. Observing from the features of the common model, the major applications are in circuit7 level analyses and simulations. Besides, the hints for device design can also be obtained by the common models due to their structure/process oriented features. In Chapter 2, the threshold7 voltage models for conventional and LDD MOSFET's have been presented, in which the implanted channel profile is approximated by a step profile, and the short7 channel effect is modeled by combining a charge sharing scheme and the superposition of the bulk depleted charges. Considering the built7 in voltages across the setp junctions, the discontinuities of the threshold voltage have been eliminated. By replacing the heavily doped concentration of the source/drain regions to lightly doped drain doping, the threshold voltages of LDD MOSFET's can be easily calculated. Although the disagreements of the threshold voltage for larger substrate biases can be observed from comparisons between the calculated and measured results. The deficiency is due to the assumption that the surface potential along the channel is constant. However, the developed threshold7 voltage moedls are still applicable for practical substrate biases. In Chapter 3, the drain7 current model for conventional MOSFET's has been derived by considering field7 dependent mobility, short7 channel threshold voltage, implanted channel profile, and constant parasitic resistance. Based on the derivations for conventional MOSFET's and taking the n-region as a buried7 channel MOSFET with a modified charge sharing scheme, the drain7 current model for LDD MOSFET's has been developed. Besides, the drain currents for conventional and LDD MOSFET's operated in the saturation region have been obtained by using one7 dimensional approximation. Using the parameters determined by a series of least7 square fittings, the calculated drain currents have been shown to satisfactorily agree with the measured data. In Chapter 4, the analytic substrate7 current models for conventional and LDD MOSFET's have been developed by using the pseudo two7 dimensional approximation in the channel and drain regions to obtain both the channel length modulation factors and the maximum electric field. By using an existing simplified substrate current formula and the developed mzximum electric field, the substrate currents of conventional/ LDD MOSFET's have been calculated. Besides, the drain current can also be self7 consistently calculated by using the I7 V moedl in Chapter 3 and the developed channel length modulation factor. Using a two7 dimensional numerical MOS device simulator, it has been shown that the accuracy of the developed maximum electric field model is acceptable for calculating the substrate currents of conventional/LDD MOSFET's. Moreover, the parameters used in the substrate7 current models can be determined by the developed optimization technique. Comparing the calculated drain and substrate currents with the experimental data measured. form the test devices with conventional/LDD MOS structures, the developed substrate7 current models have been shown to be valid for wide ranges of channel lengths and bias conditions. Furthermore, the double7 hump characteristics of LDD MOSFET's have been studied by using 27 D numerical slmulation. It has been shown that this phenomenon is due to the fact that the peak generation rate transfers from the channel/n-junction neat the drain side to the gate edge neat the source side. In Chapter 5, the analytic models for the intrinsic and extrinsic charges of conventional and LDD MOSFET's have been presented. In our developed intrinsic charge model, a new parameter has been defined to smoothly connect the intrinsic charges and capacitances at the transition between the linear and saturation regions. In our developed extrinsic charge model,the n-region of LDD MOSFET's has been modeled by three buried7 channel devices with a modified charge sharing scheme. The developed model for the n-region of LDD MOSFET's can also be applied to the n+region of conventional MOSFET's. In order to verify the accuracy of the developed analytic models for the intrinsic and extrinsic charges, a new calculation method for the intrinsic and extrinsic charges using 27 D numerical simulation has been presented. Comparisons of the calculated intrinsic and extrinsic charges between the developed analytic models and the numerical simulations have been made and satisfactory agreements are obtained. In Chapter 6, the major contributions and the proposed future researches have been described.