深次微米n通道金氧半場效電晶體之參數萃取及元件模式的新技術

Abstract

本論文探討次微米及深次微米n-型金氧半場效電晶體的參數萃取與元件模 式。每一個參數都由影響元件特性最巨的條件下萃取而來，可依序萃取所 有的結構與移動率參數。此外，短通道元件之逆短通道效應也加以深入研 究，並提出一個正確的模型以模擬此一效應，更因此導出一簡化之解析模 式。另外，本文亦導出一個退化元件的臨界電壓解析模式，此一模式由三 區域的帕松方程式解出，並考慮了二維的效應。縱觀本論文的內容，研究 主題著重於非常短通道元件的關鍵課題。本論文將針對參數萃取、元件模 擬及模式廣泛地加以深入研究。第一章將概述本論文的研究動機與簡介。 第二章將提出一個可適用於傳統式及淺摻雜洩極元件之冶金通道長度的萃 取方法，其中以常用的電阻萃取法為基礎，並配合特別的技巧消除通道長 度的不確定性及減少源╱洩極寄生電阻對臨界電壓的影響，使萃取的結果 更為準確。比較特別的是，冶金通道長度是由一個大範圍與閘極電壓有關 的有效通道長度中取一適當閘極電壓下的有效通道長度。由二維數值分析 ，可以清楚觀察到此一適當的閘極電壓與源╱洩極及通道雜質濃度有密切 的關係。因此，我們導出了一個與此三者有關的解析公式，結果顯示在萃 取冶金通道長度時，傳統式元件需要較高的閘極電壓；而淺摻雜洩極元件 則需要較低的閘極電壓。這是首次提出給定一正確的閘極電壓以萃取此兩 種電晶體之冶金通道長度的萃取方法。此外，源╱洩極寄生電阻亦可由此 萃取方法求出。第三章提出一個模型來描述元件的逆短通道效應之雜質重 新分佈。此一模型是根據已知的物理特性及電性導出，其中考慮了橫向及 垂直方向的雜質重新分佈。最重要的是，基板上的雜質空乏現象亦可由一 空乏係數來描述。模擬結果與實驗資料比較，顯示相當吻合。本文更進一 步使用二重積分簡化此一模型，可以導出一個包括逆短通道效應之臨界電 壓模式，此一模式利用四個參數，每個參數都有其物理意義，可以幫助我 們更加瞭解此一效應。此一簡單而正確的模式可以毋需太多修改，即可應 用在電路模擬中。在第四章中，我們提出一個含有局部界面電荷的元件之 臨界電壓模式，把退化的元件分成三個區域，使用二維帕松方程式解出表 面電位，並求出最低表面電位，進而導出臨界電壓模式。經過驗證，此一 模式可正確地預測未退化及退化元件之臨界電壓。此外，對於洩極引發的 能障降低效應及基極偏壓效應都可正確地涵蓋在模式中。由此可以發現， 內建電位及洩極偏壓引起的遮蔽效應對於局部界面電荷在臨界電壓的影響 十分重要。計算結果顯示，局部界面電荷的寬度、位置與密度是影響退化 元件臨界電壓的重要因數。利用二維元件模擬器，在各種條件下的模擬結 果驗證了此一模式的正確性。第五章詳述了元件參數的萃取方法，每一參 數的萃取方法都是根據此一參數影響元件特性最巨的條件下導出。測試元 件的所有參數包括元件與移動率參數都依序以所述的萃取方法得到，並放 入元件模擬器（ＳＵＭＭＯＳ）中，模擬結果顯示與測量資料十分吻合， 驗證了這些方法的正確性。由現有元件的特性加以檢討，本章提出改進元 件性能的建議，我們展示了一個元件設計的例子，其中考慮了臨界電壓的 降低、洩極引發能障降低效應、橫向電場、漏電流、轉導及飽和電流等重 要的元件性能及可靠性的相關要求。最後，在第六章中，將本論文之重要 貢獻做一整理回顧並做一總結，且展望值得延伸探討的研究方向。 This thesis focuses on the parameter extraction and device modeling techniques for submicrometer and deep submicrometer n- MOSFET's. The extraction method of each paramaters is based on its domination in the device characteristics. All the structure and mobility parameters are considered in sequence. Besides, the Reverse Short-Channel Effect(RSCE) on the threshold voltage of short-channel devices are investigated. An accurate model is proposed to simulate this effect, and a simplified analytic model can be derived. Furthermore, an analytic threshold-voltage model on the damaged MOSFET devices is derived from the 3-zones Poisson's equation with considering the 2-Deffects. This thesis focuses on the most important issues of very-short-channel MOSFET's. In this thesis, the parameter extraction, device simulation and modeling are comprehensively studied. In Chapter 1, motivation and general introduction of this thesis are given. In Chapetr 2, a new extraction algorithm for the metallurgical channel length of conventional and Lightly Doped Drain(LDD) MOSFET's is presented, which is based on the well-known resistance method with performing a special technique to eliminate the uncertainty of the channel length as well as to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgicall channel length is determined from a wide range of gate-voltage-dependent effective channel length at an adequate gate-voltage-dependent effective channel length at an adequate gate overdrive. The 2-D numerical analysis clearly shows that the adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel dopings. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to accurately extract the metallurgical channel length not oly for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm. In Chapter 3, a new physical model for doping redistribution induced by the RSCE for n-MOSFET devices is proposed. It is deduced from the well-known physical and electrical characteristics of the RSCE. This model accounts for not only the lateral but also the vertical doping redistribution. The most importance is the doping depletion effect in the bulk is also included by a depletion coefficient. Simulation results show good agreements as compared with the experimrntal data. In addition, simplifying this model by double integrations, an analytic threshold-voltage model for n-MOSFET devices with the RSCE is derived. The derived analytic threshold-voltage model introduces four parameters to describe the RSCE, each of them has its physical meaning and therefore can help us to get more insight into the RSCE. This simple and accurate model can be easily implemented into circuit simulator without major modification. In Chapter 4, a new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the 2-D Poisson's equation. Calculating the minimum surface potential,the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for not only the fresh devices but also the damaged devices. Moreover, the DIBL and substrate bias effects are also included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impactof the localized interface charges on the threshold voltage. Calculation results show that the extension, position and density of localized interface charges are the main issues to influence the threshold voltageof a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreements are obtained for various cases. In Chapter 5, the descriptions for the extraction techniques of the device parameters are illustrated. The extraction technique of each parameter is obtained according to its most important influences on the device characteristics for different devices operated under different bias conditions. All the parameters including device structure and mobility model model for a set of test devices are extracted in sequence. The whole extracted parameters are putting into a device simulator-SUMMOS and the simulation results show excellent agreements as compared with the experimental data, and the validity of the extraction techniques is verified. Device characteristics for the existing devices are examined, some comments and suggestions on improving the performance are declared. In addition, a design example for a very short-channel device is demonstrated by considering the threshold-voltage roll-off and Drain-Induced Barrier Lowering( DIBL) effects, lateral electric field, leakage current, transconductance and saturation current of the device. Finally, conclusions are given in Chapter 6, where the major contributions of this thesis and some possible future researches are proposed.