高效能的三角函數產生器設計及其在通訊系統上的應用

Abstract

在這篇論文中，我們提出了四種三角函數演算法的設計概念及硬體實現設計架構和應用。它們分別為二階查表法(TLTL)、遞迴中間插值演算法(SMPI)、16進位線上補償旋轉因子座標旋轉演算法(OSC-CORDIC)及線上計算最佳化旋轉序列座標旋轉演算法(ORS-CORDIC)。 新的二階查表三角函數演算法共需要大小約2n/4+1個字元的表及總共約2.6n個n位元的加法運算（n為輸出的棈確度），即可以同時產生正弦及餘弦函數。在遞迴中間插值演算法所設計出的三角函數產生器則適合應用在可以做管線化的架構中。在它的硬體實現中，我們分別只需要一張大小為 個字元的表（m則為所採用的近似階級）及 個n位元的加法運算即可產生單一正弦或餘弦函數。另外，我們還可以利用相同的概念，更進一步將遞迴中間插值演算法推廣到指數函數、對數函數、及雙曲線三角函數中。根據遞迴中間插值演算法的規律結構，我們更可以利用相同的一個硬體核心來同時實現上述的各種函數。 另外，由所提出的16進位線上補償旋轉因子座標旋轉演算法及線上計算最佳化旋轉序列座標旋轉演算法所設計之三角函數產生器。因為座標旋轉演算法的基本概念就是處理向量的旋轉，因此，在通訊系統中，他們特別適合運用在時脈徧移補償及快速傅立葉轉換。在它們的硬體設計架構□，兩者都只需要約2n/3個字元的表及各別需要3.5n及1.6n個n位元的加法運算就可以有效率的同時產生正弦函數、餘弦函數及比率常數的運算。 在所需運算位元長度的理論推導中發現，在0階、2階遞迴中間插值演算法、及新的CORDIC架構下，我們分別只需要 、 、及 的運算位元長度就可以得到n位元的精確度。模擬結果也確認了我們的推導結果。在16-bit的設計範例中，模擬結果表現出利用所提出的二階查表三角函數演算法及遞迴中間插值演算法的硬體實現架構中，其平均的雜訊比(signal to noise ratio)及無雜散動態範圍約(spurious-free dynamic range)都在96dB及100dBc以上。 我們將所提出二階查表法和中間插值演算法應用在軟體無線電中之頻率合成器上，而所提出的兩種座標旋轉演算法(OSC-CORDIC及ORS-CORDIC)則分別應用在802.11n/802.16e 2X2雙模多天線基頻傳收機中的時脈徧移補償和傅立葉轉換上，並且結合其它必要之的演算法架構，利用自行開發之信使基頻傳收機軟體無線電與快速原型系統晶片驗證平台(HeRMes)，實作出802.11n/802.16e 2X2雙模多天線基頻傳收機。 最後，我們利用聯電90nm低功率製程設計出2X2雙模多天線基頻傳收機之系統單晶片。其總面積為3142047μm2，而模擬在802.11n及802.16e的模式下，總消耗功率分別為288mW及387mW。

In this dissertation, four trigonometric function techniques and their applications are proposed. They are a two-level table lookup (TLTL) scheme, a successive mid-point interpolation (SMPI) algorithm, a radix-16 on-line scale factor compensation coordinate rotation digital computation algorithm (OSC-CORDIC), and an on-line optimized rotation sequence CORDIC algorithm (ORS-CORDIC). The proposed TLTL algorithm only needs a table size of about 2n/4+1 words and around 2.6n n-bit addition operations (where n is output precision) to compute both sine and cosine values simultaneously. The proposed SMPI trigonometric function generator is regular and suitable for pipelined design. It only needs a table size of words (where m is the adopted approximation order) and n-bit addition operations. Besides, it can also be applied to other elementary functions, such as exponential functions, hypertrigonometric functions, and logarithm functions. Due to the regular structure of the proposed SMPI technique, all these functions can be realized by the same computation engine. For the proposed OSC-CORDIC and ORS-CORDIC algorithms, since CORDIC algorithms was invented for vector rotation, they are suitable for clock frequency offset compensation (CFO) and fast Fourier transformer (FFT) needed in communication applications. Both algorithms require a table size of about 2n/3 words and around 3.5n and 1.6n n-bit addition operations, respectively, to compute both sine and cosine values simultaneously, including the scale-factor compensation. We also conducted theoretical analysis of finite word-length error analyses. It is concluded that only , , and bits are enough in the fixed-point operations for the proposed 0th-order, 2nd-order SMPI algorithms, and two CORDIC algorithms to achieve outputs with n-bit precision. Simulations also confirm the derived results. For the 16-bit design examples of the proposed TLTL and SMPI algorithms, they show that in average more than 96 dB of SNR and 100 dBc SFDR (spurious-free dynamic range) are achieved for the applications of digital frequency synthesizer (DDFS). The proposed TLTL and SMPI techniques are applied to DDFS designs for soft-defined-radio (SDR) systems, while the proposed OSC-CORDIC and ORS-CORDIC techniques are applied to CFO and FFT/IFFT designs, respectively, for dual-standard 802.11n/802.16e 2X2 MIMO transceiver design, and are verified with our HeRMes SDR and SoC fast prototyping platform. Finally, we implement the dual-standard 802.11n/802.16e 2X2 MIMO transceiver SoC chip based on UMC 90nm low-power cell library. The total area is 3142047μm2 and the power consumption is 288mW and 387mW in 802.11n mode and 802.16e mode from simulation, respectively.