適用於遞迴架構高點數快速傅利葉轉換之低點數快速傅利葉轉換設計之研究

Abstract

隨著利用高點數快速傅利葉轉換的應用日益增多，快速傅利葉轉換處理器的效能越來越受到重視。一般而言，為了要節省成本與降低複雜度，高點數快速傅利葉轉換會以低點數快速傅立葉轉換的遞迴架構實現的。在此論文中提出了一份適用於遞迴架構高點數快速傅利葉轉換的低點數快速傅立葉轉換設計的研究。在遞迴架構下，每次低點數快速傅立葉轉換迴圈的延遲將會是整體效能的瓶頸所在。為了要達到更低的延遲，此論文中提出了一個新的使用座標旋轉與分散式運算的快速傅立葉轉換架構。此論文還以801.11a無線網路中64點快速傅立葉轉換處理器為例，提出了硬體實現的研究。此快速傅立葉轉換處理器的規格是16位元及20MHz的產出率。我們以TSMC 0.18-um製程製作出2顆的64點快速傅立葉轉換處理器，其中一顆是以我們所提出的架構為基礎，另一顆則是以傳統的平行8點快速傅立葉轉換為基礎。經過不斷的模擬、分析及改善後，我們下了一個結論：對於遞迴架構的高點數快速傅利葉轉換處理器，最適合以平行8點快速傅立葉轉換實現。

With the growing trend on many specific applications adopting long-length FFT, the performance of FFT processors is more and more important. Generally, the long-length FFT is implemented with recursive short-length FFT in order to save the cost and complexity. This thesis presents a study on different short-length FFT designs for recursive architecture long-length FFT. Under recursive architecture, latency of each short-length FFT iteration will be the bottleneck of overall performance. A new structure with CORDIC (COordinate Rotation DIgital Computer) and DA (Distributed Arithmetic) technique is proposed in order to achieve low latency. A case study on realizing an 802.11a 64-point FFT processor is also presented. The specified FFT processor computes 16-bit input data at a throughput rate of 20MHz. The two chips, the proposed 64-point CORDIC-DA FFT processor and the other one with fully parallel 8-point FFT structure, were fabricated using TSMC 0.18-um single-poly six-metal CMOS process. After simulation, analysis, and refinement, we make a conclusion that the parallel 8-point FFT structure is most suitable for recursive architecture FFT.