適用於正交分頻多工系統之以座標旋轉架構之快速傅立葉轉換處理器

Abstract

為了設計一個具低複雜度、低成本的可變長度快速傅立葉轉換處理器以適用於多種正交分頻多工的通訊系統，本論文由演算法至架構層次研究各種關於快速傅立葉轉換的技術，並提出一個以座標旋轉架構設計的快速傅立葉轉換處理器。本論文解決了大部分以座標旋轉架構設計所面臨的問題:不有效率的旋轉因子及所需決定旋轉因子的設計複雜度與記憶體的大小。本論文所提出的方法能產生非常接近最佳的旋轉因子並使用非常小的旋轉因子記憶體，使用記憶體的大小約是現行的快速傅立葉轉換運算之轉動因子記憶體大小的1%。所實現的快速傅立葉轉換運算單元以UMC 0.18um 1P6M製程合成後最高的工作頻率為222MHz，可適用於DAB、 DVB、802.16和VDSL等多種通訊標準。所佔的面積為89263個邏輯閘，功率消耗為26.75mW。相較於一般複數乘法器架構的快速傅立葉轉換運算單元設計，能達到約略30% 速度上的提升，與約略15% 功率消耗的減少。

In order to design a low-complexity, low-cost and power efficient FFT processor module suitable for various OFDM communication systems, we study various design techniques from algorithm level to architecture level. We found that conventional multiplier-based FFT processor requires high design complexity and power consumption. CORDIC-based FFT processor seems to be a good substitution here. However, most CORDIC-based FFT processors suffer two common problems. The first one is the required long rotation sequences. On the other hand, some efficient designs need huge table to store the optimized rotation sequences. In this thesis, we propose a new CORDIC algorithm which provides a good balance between the efficiency of rotation sequences and table size for efficient sequence decision. We can generate nearly optimum rotation sequences with very small sequence table. Meanwhile, the table required for our new CORDIC algorithm is only about 1% the table size for the optimum rotation sequence and the table size required for twiddle factor ROM table in conventional FFT architectures. Besides, the architecture of our new CORDIC algorithm is very flexible. It can easily meet the computational specification of modern OFDM communication systems. For practical applications, we map the algorithm into two different architectures as design examples. The presented architectures are synthesized with synopsys Design_Complier with UMC 0.18 1P6M CMOS technology. The fastest operation frequency of our architecture is 222MHz. This can meet the computational specification of most modern OFDM-based communication systems, including DAB, DVB, 802.16 and VDSL. The gate count of the processing element base on our new CORDIC algorithm, which is implemented with 16-bit internal datapath word length, is 89263, and consumes 26.75 mW. When compared with a general multiplier-based processing element, we can achieve roughly 30% faster operation frequency with roughly 15% reduction in power consumption.