标题: | 高效能的三角函数产生器设计及其在通讯系统上的应用 Efficient Designs of Trigonometric Function Generators and Their Applications to Communication Systems |
作者: | 曲建全 Chien-Chuan Chih 陈绍基 Sau-Gee Chen 电子研究所 |
关键字: | 三角函数演算法;二阶查表法;递回中间插值演算法;16进位线上补偿旋转因子座标旋转演算法;线上计算最佳化旋转序列座标旋转演算法;信使基频传收机软体无线电与快速原型系统晶片验证平台;trigonometric function techniques;two-level table lookup;successive mid-point interpolation;radix-16 on-line scale factor compensation coordinate rotation digital computation algorithm;on-line optimized rotation sequence CORDIC algorithm;HeRMes SDR and SoC fast prototyping platform |
公开日期: | 2008 |
摘要: | 在这篇论文中,我们提出了四种三角函数演算法的设计概念及硬体实现设计架构和应用。它们分别为二阶查表法(TLTL)、递回中间插值演算法(SMPI)、16进位线上补偿旋转因子座标旋转演算法(OSC-CORDIC)及线上计算最佳化旋转序列座标旋转演算法(ORS-CORDIC)。 新的二阶查表三角函数演算法共需要大小约2n/4+1个字元的表及总共约2.6n个n位元的加法运算(n为输出的棈确度),即可以同时产生正弦及余弦函数。在递回中间插值演算法所设计出的三角函数产生器则适合应用在可以做管线化的架构中。在它的硬体实现中,我们分别只需要一张大小为 个字元的表(m则为所采用的近似阶级)及 个n位元的加法运算即可产生单一正弦或余弦函数。另外,我们还可以利用相同的概念,更进一步将递回中间插值演算法推广到指数函数、对数函数、及双曲线三角函数中。根据递回中间插值演算法的规律结构,我们更可以利用相同的一个硬体核心来同时实现上述的各种函数。 另外,由所提出的16进位线上补偿旋转因子座标旋转演算法及线上计算最佳化旋转序列座标旋转演算法所设计之三角函数产生器。因为座标旋转演算法的基本概念就是处理向量的旋转,因此,在通讯系统中,他们特别适合运用在时脉徧移补偿及快速傅立叶转换。在它们的硬体设计架构□,两者都只需要约2n/3个字元的表及各别需要3.5n及1.6n个n位元的加法运算就可以有效率的同时产生正弦函数、余弦函数及比率常数的运算。 在所需运算位元长度的理论推导中发现,在0阶、2阶递回中间插值演算法、及新的CORDIC架构下,我们分别只需要 、 、及 的运算位元长度就可以得到n位元的精确度。模拟结果也确认了我们的推导结果。在16-bit的设计范例中,模拟结果表现出利用所提出的二阶查表三角函数演算法及递回中间插值演算法的硬体实现架构中,其平均的杂讯比(signal to noise ratio)及无杂散动态范围约(spurious-free dynamic range)都在96dB及100dBc以上。 我们将所提出二阶查表法和中间插值演算法应用在软体无线电中之频率合成器上,而所提出的两种座标旋转演算法(OSC-CORDIC及ORS-CORDIC)则分别应用在802.11n/802.16e 2X2双模多天线基频传收机中的时脉徧移补偿和傅立叶转换上,并且结合其它必要之的演算法架构,利用自行开发之信使基频传收机软体无线电与快速原型系统晶片验证平台(HeRMes),实作出802.11n/802.16e 2X2双模多天线基频传收机。 最后,我们利用联电90nm低功率制程设计出2X2双模多天线基频传收机之系统单晶片。其总面积为3142047μm2,而模拟在802.11n及802.16e的模式下,总消耗功率分别为288mW及387mW。 In this dissertation, four trigonometric function techniques and their applications are proposed. They are a two-level table lookup (TLTL) scheme, a successive mid-point interpolation (SMPI) algorithm, a radix-16 on-line scale factor compensation coordinate rotation digital computation algorithm (OSC-CORDIC), and an on-line optimized rotation sequence CORDIC algorithm (ORS-CORDIC). The proposed TLTL algorithm only needs a table size of about 2n/4+1 words and around 2.6n n-bit addition operations (where n is output precision) to compute both sine and cosine values simultaneously. The proposed SMPI trigonometric function generator is regular and suitable for pipelined design. It only needs a table size of words (where m is the adopted approximation order) and n-bit addition operations. Besides, it can also be applied to other elementary functions, such as exponential functions, hypertrigonometric functions, and logarithm functions. Due to the regular structure of the proposed SMPI technique, all these functions can be realized by the same computation engine. For the proposed OSC-CORDIC and ORS-CORDIC algorithms, since CORDIC algorithms was invented for vector rotation, they are suitable for clock frequency offset compensation (CFO) and fast Fourier transformer (FFT) needed in communication applications. Both algorithms require a table size of about 2n/3 words and around 3.5n and 1.6n n-bit addition operations, respectively, to compute both sine and cosine values simultaneously, including the scale-factor compensation. We also conducted theoretical analysis of finite word-length error analyses. It is concluded that only , , and bits are enough in the fixed-point operations for the proposed 0th-order, 2nd-order SMPI algorithms, and two CORDIC algorithms to achieve outputs with n-bit precision. Simulations also confirm the derived results. For the 16-bit design examples of the proposed TLTL and SMPI algorithms, they show that in average more than 96 dB of SNR and 100 dBc SFDR (spurious-free dynamic range) are achieved for the applications of digital frequency synthesizer (DDFS). The proposed TLTL and SMPI techniques are applied to DDFS designs for soft-defined-radio (SDR) systems, while the proposed OSC-CORDIC and ORS-CORDIC techniques are applied to CFO and FFT/IFFT designs, respectively, for dual-standard 802.11n/802.16e 2X2 MIMO transceiver design, and are verified with our HeRMes SDR and SoC fast prototyping platform. Finally, we implement the dual-standard 802.11n/802.16e 2X2 MIMO transceiver SoC chip based on UMC 90nm low-power cell library. The total area is 3142047μm2 and the power consumption is 288mW and 387mW in 802.11n mode and 802.16e mode from simulation, respectively. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT008811838 http://hdl.handle.net/11536/55223 |
显示于类别: | Thesis |