在超大型積體數位電路的障礙分析

Abstract

This dissertation analyzes the equivalence and dominance fault relationships in COMS combinational circuits as well as in sequential circuits. (1)For CMOS combinationalcircuits, a new logic element, My_Box,is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits. My_Box representation can be used for all types of CMOS logics. A procedure is described to transform a transistor level CMOS circuit to a gate level equivalent circuit which is composed of AND, OR and the My_Box logic elements. A fault collapsing procedure is also derived to determine the representative set of prime faults for the transformed gate level ciruit. By applying this procedure to 10 benchmark circuits which are implemented in the fully-CMOS circuit, the total number of faults can be reduced approximately by 85%. (2) For sequential curcuits, the relationships between faults in gates and in fanouts are analyzed. It shows that only "self-hiding"or "delayed-reconvergence" makes a pair of faults in a gate which are combinationally dominant and dominated be not sequentially dominant and dominated and only the phenomenon of different propagation paths with respect to a fanout reconverging with different inversion parities may invalidate the dominance relationships of faults at the fanout which are valid in a a single fanout. Another fault collapsing procedure is proposed to collapse faults in synchronous sequential circuits. The procedure has been applied to the 31 benchmark sequential circuits, and results show that 43% of the original total faults is collapsed. A path-check criterion and a procedure are derived to check the validity of the dominance relationships of fanout faults in a circuit and an advanced fault collapsing procedure is proposed for synchronous and asynchronous sequential circuits. By applying this procedure, the collapsed target faults used for test generation and fualt simulation can be further reduced. 本論文分析CMOS組合邏輯和序向邏輯電路的對等和優勢障礙關係。(1) 對於CMOS組合 邏輯電路，提出一個新定義的邏輯閘，My-Box, 來表示線障礙和電晶體障礙和一個將 電晶體電路轉換成閘級等效電路的程序。My-Box可用來表示所有的CMOS邏輯電路。另 外亦提出一個合併障礙的方法，它已應用到10個標準組合邏輯電路，能將障礙數目減 低到原總障礙數目的百分之十五。(2) 對於序向邏輯電路，我們分析了障礙在閘及扇 出上的關係。根據我們的分析，儘有′自我隱藏′或′延遲收斂′會破壞原障礙在閘 上的關係；以及儘有不同極性的收斂路徑會破壞原障礙在扇出上的關係。對於同步序 向電路，能將障礙數目減低到原總障礙數目的百分之四十三。提出一個路徑檢查準則 和方法來檢驗障礙在扇出上的關係是否仍存在；並且提出一個更深入合併障礙的和方 法，它可應用到同步以及非同步序向邏輯電路，並能將障礙數目大大地減低。