Identification of robust untestable path delay faults

Abstract

This paper presents a theoretical analysis to identify robust untestable path delay faults. Firstly, it classifies the reconvergence of paths into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure is suitable for distributed processing by circuit partitioning to reduce the computation time and required memory. Experimental results on ISCAS 85' benchmark circuits show that the robust untestable faults occupy a high percentage of the total faults and high speedup can be obtained for distributed processing. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit.