標題: | Identification of robust untestable path delay faults |
作者: | Wu, WC Lee, CL Chen, JE 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | path delay fault;robust delay testing;untestable fault |
公開日期: | 1-九月-1997 |
摘要: | This paper presents a theoretical analysis to identify robust untestable path delay faults. Firstly, it classifies the reconvergence of paths into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure is suitable for distributed processing by circuit partitioning to reduce the computation time and required memory. Experimental results on ISCAS 85' benchmark circuits show that the robust untestable faults occupy a high percentage of the total faults and high speedup can be obtained for distributed processing. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit. |
URI: | http://hdl.handle.net/11536/355 |
ISSN: | 0253-3839 |
期刊: | JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS |
Volume: | 20 |
Issue: | 5 |
起始頁: | 549 |
結束頁: | 559 |
顯示於類別: | 期刊論文 |